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? 2004 microchip technology inc. preliminary ds41249a PIC16F785 data sheet 20-pin flash-based 8-bit cmos microcontroller with two-phase asychronous feedback pwm, dual high-speed comparators and dual operational amplifiers
ds41249a-page ii preliminary ? 2004 microchip technology inc. information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. no representation or warranty is given and no liability is assumed by microchip technol ogy incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of mi crochip?s products as critical components in life support syst ems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or ot herwise, under any intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic, and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, mxdev, mxlab, picmaster, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, migratable memory, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, rflab, rfpicdem, select mode, smart serial, smarttel and total endurance ar e trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2004, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified.
? 2004 microchip technology inc. preliminary ds41249a-page 1 PIC16F785 high-performance risc cpu only 35 instructions to learn: - all single-cycle instructions except branches operating speed: - dc ? 20 mhz oscillator/clock input - dc ? 200 ns instruction cycle interrupt capability 8-level deep hardware stack direct, indirect and relative addressing modes special microcontroller features precision internal oscillator: - factory calibrated to 1% - software selectable frequency range of 8 mhz to 32 khz - software tunable - two-speed start-up mode - crystal fail detect for critical applications - clock mode switching during operation for power savings power-saving sleep mode wide operating voltage range (2.0v-5.5v) industrial and extended temperature range power-on reset (por) power-up timer (pwrt) and oscillator start-up timer (ost) brown-out reset (bor) with software control option enhanced low-current watchdog timer (wdt) with on-chip oscillator (software selectable nominal 268 seconds with full prescaler) with software enable multiplexed master clear with pull-up/input pin programmable code protection high-endurance flash/eeprom cell: - 100,000 write flash endurance - 1,000,000 write eeprom endurance - flash/data eeprom retention: > 40 years low-power features standby current: - 30 na @ 2.0v, typical operating current: -8.5 a @ 32 khz, 2.0v, typical -100 a @ 1 mhz, 2.0v, typical watchdog timer current: -1 a @ 2.0v, typical timer1 oscillator current: -2 a @ 32 khz, 2.0v, typical peripheral features high-speed comparator module with: - two independent analog comparators - programmable on-chip voltage reference (cv ref ) module (% of v dd ) - 1.2v band gap reference - comparator inputs and outputs externally accessible - < 40 ns propagation delay - 2 mv offset, typical operational amplifier module with 2 independent op amps: - 3 mhz gbwp, typical - all i/o pins externally accessible two-phase asychronous feedback pwm mod- ule: - complementary output with programmable overlap/dead band delay - infinite resolution analog duty cycle - sync output/input for multi-phase pwm -f osc /2 maximum pwm frequency a/d converter: - 10-bit resolution and 14 channels (2 internal) 17 i/o pins and 1 input-only pin: - high-current source/sink for direct led drive - interrupt-on-pin change - individually programmable weak pull-ups timer0: 8-bit timer/counter with 8-bit programmable prescaler enhanced timer1: - 16-bit timer/counter with prescaler - external gate input mode - option to use osc1 and osc2 in lp mode as timer1 oscillator, if intosc mode selected timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler capture, compare, pwm module: - 16-bit capture, max resolution 12.5 ns - compare, max resolution 200 ns - 10-bit pwm with 1 output channel, max frequency 20 khz in-circuit serial programming tm (icsp tm ) via two pins 20-pin flash-based 8-bit cmos microcontroller
PIC16F785 ds41249a-page 2 preliminary ? 2004 microchip technology inc. pin diagram device program memory data memory i/o 10-bit a/d (ch) operational amplifiers comparators ccp 2 phase pwm timers 8/16-bit flash (words) sram (bytes) eeprom (bytes) PIC16F785 2048 128 256 17+1 12 2 2 1 1 2/1 20-pin pdip, soic, ssop v dd ra5/t1cki/osc1/clkin ra4/an3/t1g/osc2/clkout ra3/mclr /v pp rc5/ccp1 rc4/c2out/ph2 rc3/an7/c12in3-/op1 rc6/an8/op1- rc7/an9/op1+ rb7/sync v ss ra0/an0/c1in+/icspdat ra1/an1/c12in0-/v ref /icspclk ra2/an2/t0cki/int/c1out rc0/an4/c2in+ rc1/an5/c12in1-/ph1 rc2/an6/c12in2-/op2 rb4/an10/op2- rb5/an11/op2+ rb6 PIC16F785 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11
? 2004 microchip technology inc. preliminary ds41249a-page 3 PIC16F785 table of contents 1.0 device overview ............................................................................................................. ............................................................. 5 2.0 memory organization ......................................................................................................... .......................................................... 9 3.0 clock sources ............................................................................................................... ............................................................. 23 4.0 i/o ports ................................................................................................................... .................................................................. 33 5.0 timer0 module ............................................................................................................... ............................................................ 47 6.0 timer1 module with gate control............................................................................................. .................................................. 49 7.0 timer2 module ............................................................................................................... ............................................................ 53 8.0 capture/compare/pwm (ccp) module ............................................................................................ ......................................... 55 9.0 comparator module........................................................................................................... ......................................................... 61 10.0 voltage references......................................................................................................... ........................................................... 69 11.0 operational amplifier (opa) module ......................................................................................... ................................................. 73 12.0 analog-to-digital converter (a/d) module................................................................................... ............................................... 77 13.0 two-phase pwm .............................................................................................................. ......................................................... 87 14.0 data eeprom memory ......................................................................................................... .................................................... 99 15.0 special features of the cpu................................................................................................ .................................................... 103 16.0 instruction set summary .................................................................................................... ...................................................... 123 17.0 development support........................................................................................................ ....................................................... 133 18.0 electrical specifications.................................................................................................. .......................................................... 139 19.0 packaging information...................................................................................................... ........................................................ 161 appendix a: data sheet revision history........................................................................................ .................................................. 165 appendix b: migrating from other picmicro? devices............................................................................. ......................................... 165 index .......................................................................................................................... ........................................................................ 167 on-line support................................................................................................................ ................................................................. 173 systems information and upgrade hot line ....................................................................................... ............................................... 173 reader response ................................................................................................................ .............................................................. 174 product identification system .................................................................................................. .......................................................... 175 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@mail.microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/doc umentation issues become known to us, we will publis h an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particul ar device, please check with one of the following: microchip?s worldwide web site; http://www.microchip.com your local microchip sales office (see last page) the microchip corporate literatu re center; u.s. fax: (480) 792-7277 when contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (inclu de literature number) you are using. customer notification system register on our web site at www.microchip.com/cn to receive the most current information on all of our products.
PIC16F785 ds41249a-page 4 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds41249a-page 5 PIC16F785 1.0 device overview this document contains device specific information for the PIC16F785. additional information may be found in the picmicro ? mid-range reference manual (ds33023), which may be obtained from your local microchip sales representative or downloaded from the microchip web site. the reference manual should be considered a complementary document to this data sheet and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules. the PIC16F785 is covered by this data sheet. it is available in 20-pin pdip, soic and ssop packages. figure 1-1 shows a block diagram of the PIC16F785 device. table 1-1 shows the pinout description. figure 1-1: pic16f 785 block diagram flash program memory 13 data bus 8 14 program bus instruction reg program counter ram file registers direct addr 7 ram addr 9 addr mux indirect addr fsr reg status reg mux alu w reg instruction decode & control timing generation osc1/clkin osc2/clkout porta 8 8 8 3 8-level stack 128 2k x 14 bytes (13-bit) power-up timer oscillator start-up timer power-on reset watchdog timer mclr v ss brown-out detect 2 analog timer0 timer1 data eeprom 256 bytes eedata eeaddr comparators an0 an1 an2 an3 c1in- c1in+ c1out t0cki int t1cki configuration internal oscillator v ref t1g portb an4 an5 an6 an7 v dd 8 timer2 c2in- c2in+ c2out ccp block ccp1 an3 an8 an9 an10 an11 rb4 rb5 rb6 rb7 portc rc0 rc1 rc2 rc3 rc4 rc5 rc6 rc7 ra0 ra1 ra2 ra3 ra4 ra5 analog-to-digital converter op1 op1+ op1- op2 op2+ op2- dual op amps ph1 ph2 sync 2 phase pwm voltage reference
PIC16F785 ds41249a-page 6 preliminary ? 2004 microchip technology inc. table 1-1: PIC16F785 pinout description name pin function input type output type description ra0/an0/c1in+/icspdat 19 ra0 ttl cmos porta i/o w/ prog. pull-up and interrupt-on-change an0 an ? a/d channel 0 input c1in+ an ? comparator 1 non-inverting input icspdat st cmos serial programming data i/o ra1/an1/c12in0-/v ref /icspclk 18 ra1 ttl cmos porta i/o w/ prog. pull-up and interrupt-on-change an1 an ? a/d channel 1 input c12in0- an ? comparator 1and 2 inverting input v ref an an external voltage reference for a/d, buffered reference output icspclk st ? serial programming clock ra2/an2/t0cki/int/c1out 17 ra2 st cmos porta i/o w/ prog. pull-up and interrupt-on-change an2 an ? a/d channel 2 input t0cki st ? timer0 clock input int st ? external interrupt c1out ? cmos comparator 1 output ra3/mclr /v pp 4 ra3 ttl ? porta input w/ prog. pull-up and interrupt-on-change mclr st ? master clear w/ internal pull-up v pp hv ? programming voltage ra4/an3/t1g/osc2/clkout 3 ra4 ttl cmos porta i/o w/ prog. pull-up and interrupt-on-change an3 an ? a/d channel 3 input t1g st ? timer1 gate osc2 ? xtal crystal/resonator clkout ? cmos f osc /4 output ra5/t1cki/osc1/clkin 2 ra5 ttl cmos porta i/o w/ prog. pull-up and interrupt-on-change t1cki st ? timer1 clock osc1 xtal ? crystal/resonator clkin st ? external clock input/rc oscillator connection rb4/an10/op2- 13 rb4 ttl cmos portb i/o an10 an ? a/d channel 10 input op2- ? an op amp 2 inverting input rb5/an11/op2+ 12 rb5 ttl cmos portb i/o an11 an ? a/d channel 11 input op2+ ? an op amp 2 non-inverting input rb6 11 rb6 ttl od portb i/o. open drain output rb7/sync 10 rb7 ttl cmos portb i/o sync st cmos master pwm sync output or slave pwm sync input rc0/an4/c2in+ 16 rc0 ttl cmos portc i/o an4 an ? a/d channel 4 input c2in+ an ? comparator 2 non-inverting input rc1/an5/c12in1-/ph1 15 rc1 ttl cmos portc i/o an5 an ? a/d channel 5 input c12in1- an ? comparator 1 and 2 inverting input ph1 ? cmos pwm phase 1 output rc2/an6/c12in2-/op2 14 rc2 ttl cmos portc i/o an6 an ? a/d channel 6 input c12in2- an ? comparator 1 and 2 inverting input op2 ? an op amp 2 output rc3/an7/c12in3-/op1 7 rc3 ttl cmos portc i/o an7 an ? a/d channel 7 input c12in3- an ? comparator 1 and 2 inverting input op1 ? an op amp 1 output
? 2004 microchip technology inc. preliminary ds41249a-page 7 PIC16F785 rc4/c2out/ph2 6 rc4 ttl cmos portc i/o c2out ? cmos comparator 2 output ph2 ? cmos pwm phase 2 output rc5/ccp1 5 rc5 ttl cmos portc i/o ccp1 st cmos capture input/compare output rc6/an8/op1- 8 rc6 ttl cmos portc i/o an8 an ? a/d channel 8 input op1- an ? op amp 1 inverting input rc7/an9/op1+ 9 rc7 cmos portc i/o an9 an ? a/d channel 9 input op1+ an ? op amp 1 non-inverting input v ss 20 v ss power ? ground reference v dd 1v dd power ? positive supply legend: ttl = ttl input buffer, st = schmitt trigger input buffe r, an = analog, od = open drain output, hv = high voltage table 1-1: PIC16F785 pinout description (continued) name pin function input type output type description
PIC16F785 ds41249a-page 8 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds41249a-page 9 PIC16F785 2.0 memory organization 2.1 program memory organization the PIC16F785 has a 13-bit program counter capable of addressing an 8k x 14 program memory space. only the first 2k x 14 (0000h?07ffh) for the PIC16F785 is physically implemented. accessing a location above these boundaries will cause a wrap around within the first 2k x 14 space. the reset vector is at 0000h and the interrupt vector is at 0004h (see figure 2-1). figure 2-1: program memory map and stack for the PIC16F785 2.2 data memory organization the data memory (see figure 2-2) is partitioned into four banks, which contain the general purpose registers (gpr) and the special function registers (sfr). the special function registers are located in the first 32 locations of each bank. register locations 20h ? 7fh in bank 0 and a0h ? bfh in bank 1 are general purpose registers, implemented as static ram. the last sixteen register locations in bank 1 (f0h ? ffh), bank 2 (170h ? 17fh), and bank 3 (1f0h ? 1ffh) point to addresses 70h ? 7fh in bank 0. all other ram is unimplemented and returns ? 0 ? when read. seven address bits are required to access any location in a data memory bank. two additional bits are required to access the four banks. when data memory is accessed directly, the seven least significant address bits are contained within the opcode and the two most significant bits are contained in the status register. rp0 and rp1 (status<5> and status<6>) are the two most significant data memory address bits and are also known as the bank select bits. table 2-1 lists how to access the four banks of registers. 2.2.1 general purpose register file the register file banks are organized as 128 x 8 in the PIC16F785. each register is accessed, either directly, by seven address bits within the opcode, or indirectly, through the file select register, fsr. when the fsr is used to access data memory, the eight least signifi- cant data memory address bits are contained in the fsr and the ninth most significant address bit is con- tained in the irp bit (status<7>) of the status register. (see section 2.4 ?indirect addressing, indf and fsr registers? ). 2.2.2 special function registers the special function registers are registers used by the cpu and peripheral functions for controlling the desired operation of the device (see table 2-2). these registers are static ram. the special registers can be classified into two sets: core and peripheral. the special function registers associated with the ?core? are described in this section. those related to the operation of the peripheral features are described in the section of that peripheral feature. pc<12:0> 13 000h 0004 0005 07ffh 0800h 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program memory call, return retfie, retlw stack level 2 table 2-1: bank selection rp1 rp0 bank0 0 0 bank1 0 1 bank2 1 0 bank3 1 1
PIC16F785 ds41249a-page 10 preliminary ? 2004 microchip technology inc. figure 2-2: data memory map of the PIC16F785 indirect addr. (1) 00h indirect addr. (1) 80h indirect addr. (1) 100h indirect addr. (1) 180h tmr0 01h option_reg 81h tmr0 101h option_reg 181h pcl 02h pcl 82h pcl 102h pcl 182h status 03h status 83h status 103h status 183h fsr 04h fsr 84h fsr 104h fsr 184h porta 05h trisa 85h porta 105h trisa 185h portb 06h trisb 86h portb 106h trisb 186h portc 07h trisc 87h portc 107h trisc 187h 08h 88h 108h 188h 09h 89h 109h 189h pclath 0ah pclath 8ah pclath 10ah pclath 18ah intcon 0bh intcon 8bh intcon 10bh intcon 18bh pir1 0ch pie1 8ch 10ch 18ch 0dh 8dh 10dh 18dh tmr1l 0eh pcon 8eh 10eh 18eh tmr1h 0fh osccon 8fh 10fh 18fh t1con 10h osctune 90h pwmcon1 110h 190h tmr2 11h ansel0 91h pwmcon0 111h 191h t2con 12h pr2 92h pwmclk 112h 192h ccpr1l 13h ansel1 93h pwmph1 113h 193h ccpr1h 14h 94h pwmph2 114h 194h ccp1con 15h wpua 95h 115h 195h 16h ioca 96h 116h 196h 17h 97h 117h 197h wdtcon 18h refcon 98h 118h 198h 19h vrcon 99h cm1con0 119h 199h 1ah eedata 9ah cm2con0 11ah 19ah 1bh eeadr 9bh cm2con1 11bh 19bh 1ch eecon1 9ch opa1con 11ch 19ch 1dh eecon2 (1) 9dh opa2con 11dh 19dh adresh 1eh adresl 9eh 11eh 19eh adcon0 1fh adcon1 9fh 11fh 19fh general purpose register 96 bytes 20h general purpose register 32 bytes a0h bfh 120h 1a0h 6fh c0h efh 16fh 1efh 70h accesses bank 0 f0h accesses bank 0 170h accesses bank 0 1f0h 7fh ffh 17fh 1ffh bank 0 bank1 bank2 bank3 unimplemented data memory locations, read as ?0?. note 1: not a physical register. file address file address file address file address
? 2004 microchip technology inc. preliminary ds41249a-page 11 PIC16F785 table 2-2: PIC16F785 special function registers summary bank 0 addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor page bank 0 00h indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx 22,110 01h tmr0 timer0 module?s register xxxx xxxx 47,110 02h pcl program counter's (pc) least significant byte 0000 0000 21,110 03h status irp rp1 rp0 to pd z dc c 0001 1xxx 15,110 04h fsr indirect data memory address pointer xxxx xxxx 22,110 05h porta (1) ? ? ra5 ra4 ra3 ra2 ra1 ra0 --x0 x000 33,110 06h portb (1) rb7 rb6 rb5 rb4 ? ? ? ? xx00 ---- 40,110 07h portc (1) rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 00xx 0000 43,110 08h ? unimplemented ? ? 09h ? unimplemented ? ? 0ah pclath ? ? ? write buffer for upper 5 bits of program counter ---0 0000 21,110 0bh intcon gie peie t0ie inte raie t0if intf raif 0000 0000 17,110 0ch pir1 eeif adif ccp1if c2if c1if osfif tmr2if tmr1if 0000 0000 19,110 0dh ? unimplemented ? ? 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 xxxx xxxx 49,110 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 xxxx xxxx 49,110 10h t1con t1ginv tmr1ge t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 51,110 11h tmr2 timer2 module register 0000 0000 53,110 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 53,110 13h ccpr1l capture/compare/pwm register1 low byte xxxx xxxx 55,110 14h ccpr1h capture/compare/pwm register1 high byte xxxx xxxx 55,110 15h ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 55,110 16h ? unimplemented ? ? 17h ? unimplemented ? ? 18h wdtcon ? ? ? wdtps3 wdtps2 wdtps1 wdtps0 swdten ---0 1000 118,110 19h ? unimplemented ? ? 1ah ? unimplemented ? ? 1bh ? unimplemented ? ? 1ch ? unimplemented ? ? 1dh ? unimplemented ? ? 1eh adresh most significant 8 bits of the left justified a/d result or 2 bits of right justified result xxxx xxxx 79,110 1fh adcon0 adfm vcfg chs3 chs2 chs1 chs0 go/done adon 0000 0000 81,110 legend: ? = unimplemented locations read as ? 0 ?, u = unchanged, x = unknown, q = value depends on condition. shaded = unimplemented note 1: port pins with analog functions controlled by the ansel0 and ansel1 registers will read ? 0 ? immediately after a reset even though the data latches are either undefined (por) or unchanged (other resets).
PIC16F785 ds41249a-page 12 preliminary ? 2004 microchip technology inc. table 2-3: PIC16F785 special function registers summary bank 1 addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor page bank 1 80h indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx 22,110 81h option_reg rapu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 16,110 82h pcl program counter's (pc) least significant byte 0000 0000 21,110 83h status irp rp1 rp0 to pd z dc c 0001 1xxx 15,110 84h fsr indirect data memory address pointer xxxx xxxx 22,110 85h trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 34,110 86h trisb trisb7 trisb6 trisb5 trisb4 ? ? ? ? 1111 ---- 40,110 87h trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 43,110 88h ? unimplemented ? ? 89h ? unimplemented ? ? 8ah pclath ? ? ? write buffer for upper 5 bits of program counter ---0 0000 21,110 8bh intcon gie peie t0ie inte raie t0if intf raif 0000 0000 17,110 8ch pie1 eeie adie ccp1ie c2ie c1ie osfie tmr2ie tmr1ie 0000 0000 18,110 8dh ? unimplemented ? ? 8eh pcon ? ? ?sboren ? ?por bor ---1 --qq 20,110 8fh osccon ? ircf2 ircf1 ircf0 osts (1) hts lts scs -110 q000 32,110 90h osctune ? ? ? tun4 tun3 tun2 tun1 tun0 ---0 0000 27,110 91h ansel0 ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 1111 1111 80,110 92h pr2 timer2 module period register 1111 1111 53,110 93h ansel1 ? ? ? ? ans11 ans10 ans9 ans8 ---- 1111 80,111 94h ? unimplemented ? ? 95h wpua ? ? wpua5 wpua4 wpua3 (2) wpua2 wpua1 wpua0 --11 1111 34,111 96h ioca ? ? ioca5 ioca4 ioca3 ioca2 ioca1 ioca0 --00 0000 35,111 97h ? unimplemented ? ? 98h refcon ? ? bgst vrbb vren vroe cvroe ? --00 000- 71,111 99h vrcon c1vren c2vren vrr ? vr3 vr2 vr1 vr0 000- 0000 70,111 9ah eedat eedat7 eedat6 eedat5 eedat4 eedat3 eedat2 eedat1 eedat0 0000 0000 99,111 9bh eeadr eeadr7 eeadr6 eeadr5 eeadr4 eeadr3 eeadr2 eeadr1 eeadr0 0000 0000 99,111 9ch eecon1 ? ? ? ? wrerr wren wr rd ---- x000 100,111 9dh eecon2 eeprom control register 2 (not a physical register) ---- ---- 100,111 9eh adresl least significant 2 bits of the left justified result or 8 bits of the right justified result xxxx xxxx 78,111 9fh adcon1 ? adcs2 adcs1 adcs0 ? ? ? ? -000 ---- 81,111 legend: ? = unimplemented locations read as ? 0 ?, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented note 1: osts bit osccon <3> reset to ? 0 ? with dual speed start-up and lp, hs, or xt selected as the oscillator. 2: ra3 pull-up is enabled when mclre is ? 1 ? in configuration word.
? 2004 microchip technology inc. preliminary ds41249a-page 13 PIC16F785 table 2-4: PIC16F785 special function registers summary bank 2 addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor page bank 2 100h indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx 22,110 101h tmr0 timer0 module?s register xxxx xxxx 47,110 102h pcl program counter's (pc) least significant byte 0000 0000 21,110 103h status irp rp1 rp0 to pd z dc c 0001 1xxx 15,110 104h fsr indirect data memory address pointer xxxx xxxx 22,110 105h porta (1) ? ? ra5 ra4 ra3 ra2 ra1 ra0 --x0 x000 33,110 106h portb (1) rb7 rb6 rb5 rb4 ? ? ? ? xx00 ---- 40,110 107h portc (1) rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 00xx 0000 43,110 108h ? unimplemented ? ? 109h ? unimplemented ? ? 10ah pclath ? ? ? write buffer for upper 5 bits of program counter ---0 0000 21,110 10bh intcon gie peie t0ie inte raie t0if intf raif 0000 0000 17,110 10ch ? unimplemented ? ? 10dh ? unimplemented ? ? 10eh ? unimplemented ? ? 10fh ? unimplemented ? ? 110h pwmcon1 ovrlp comod1 comod0 cmdly4 cmdly3 cmdly2 cmdly1 cmdly0 0000 0000 95,111 111h pwmcon0 prsen pasen blank2 blank1 sync1 sync0 ph2en ph1en 0000 0000 89,111 112h pwmclk pwmase pwmp1 pwmp0 per4 per3 per2 per1 per0 0000 0000 90,111 113h pwmph1 pol c2en c1en ph4 ph3 ph2 ph1 ph0 0000 0000 91,111 114h pwmph2 pol c2en c1en ph4 ph3 ph2 ph1 ph0 0000 0000 92,111 115h ? unimplemented ? ? 116h ? unimplemented ? ? 117h ? unimplemented ? ? 118h ? unimplemented ? ? 119h cm1con0 c1on c1out c1oe c1pol c1sp c1r c1ch1 c1ch0 0000 0000 63,111 11ah cm2con0 c2on c2out c2oe c2pol c2sp c2r c2ch1 c2ch0 0000 0000 65,111 11bh cm2con1 mc1out mc2out ? ? ? ? t1gss c2sync 00-- --10 66,111 11ch opa1con opaon ? ? ? ? ? ? ? 0--- ---- 74,111 11dh opa2con opaon ? ? ? ? ? ? ? 0--- ---- 74,111 11eh ? unimplemented ? ? 11fh ? unimplemented ? ? legend: ? = unimplemented locations read as ? 0 ?, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented note 1: port pins with analog functions controlled by the ansel0 and ansel1 registers will read ? 0 ? immediately after a reset even though the data latches are either undefined (por) or unchanged (other resets).
PIC16F785 ds41249a-page 14 preliminary ? 2004 microchip technology inc. table 2-5: PIC16F785 special function registers summary bank 3 addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor page bank 3 180h indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx 22,110 181h option_reg rapu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 16,110 182h pcl program counter's (pc) least significant byte 0000 0000 21,110 183h status irp rp1 rp0 to pd z dc c 0001 1xxx 15,110 184h fsr indirect data memory address pointer xxxx xxxx 22,110 185h trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 34,110 186h trisb trisb7 trisb6 trisb5 trisb4 ? ? ? ? 1111 ---- 40,110 187h trisc trisc7 trisc6 trisc5 tri sc4 trisc3 trisc2 trisc1 trisc0 1111 1111 43,110 188h ? unimplemented ? ? 189h ? unimplemented ? ? 18ah pclath ? ? ? write buffer for upper 5 bits of program counter ---0 0000 21,110 18bh intcon gie peie t0ie inte raie t0if intf raif 0000 0000 17,110 18ch pie1 eeie adie ccp1ie c2ie c1ie osfie tmr2ie tmr1ie 0000 0000 18,110 18dh ? unimplemented ? ? 18eh ? unimplemented ? ? 18fh ? unimplemented ? ? 190h ? unimplemented ? ? 191h ? unimplemented ? ? 192h ? unimplemented ? ? 193h ? unimplemented ? ? 194h ? unimplemented ? ? 195h ? unimplemented ? ? 196h ? unimplemented ? ? 197h ? unimplemented ? ? 198h ? unimplemented ? ? 199h ? unimplemented ? ? 19ah ? unimplemented ? ? 19bh ? unimplemented ? ? 19ch ? unimplemented ? ? 19dh ? unimplemented ? ? 19eh ? unimplemented ? ? 19fh ? unimplemented ? ? legend: ? = unimplemented locations read as ? 0 ?, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
? 2004 microchip technology inc. preliminary ds41249a-page 15 PIC16F785 2.2.2.1 status register the status register, shown in register 2-1, contains: the arithmetic status of the alu the reset status the bank select bits for data memory (sram) the status register can be the destination for any instruction, like any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is dis- abled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register, because these instructions do not affect any status bits. for other instructions not affecting any status bits, see the ?instruction set summary?. register 2-1: status ? status register (address: 03h or 83h) note: the c and dc bits operate as a borrow and digit borrow out bit, respectively, in subtraction. see the sublw and subwf instructions for examples. r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd z dc c bit 7 bit 0 bit 7 irp: register bank select bit (used for indirect addressing) 1 = bank 2,3 (100h ? 1ffh) 0 = bank 0,1 (00h ? ffh) bit 6-5 rp1:rp0: register bank select bits (used for direct addressing) 11 = bank 3 (180h ? 1ffh) 10 = bank 2 (100h ? 17fh) 01 = bank 1 (80h ? ffh) 00 = bank 0 (00h ? 7fh) bit 4 to : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3 pd: power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/bo rrow bit ( addwf , addlw,sublw,subwf instructions) (1) for borrow, the polarity is reversed. 1 = a carry-out from the 4th low-order bit of the result occurred 0 = no carry-out from the 4th low-order bit of the result bit 0 c: carry/bo rrow bit ( addwf , addlw, sublw, subwf instructions) (1) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: for bo rrow , the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high-order or low-order bit of the source register. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC16F785 ds41249a-page 16 preliminary ? 2004 microchip technology inc. 2.2.2.2 option register the option register is a readable and writable register, which contains various control bits to configure: tmr0/wdt prescaler external ra2/int interrupt tmr0 weak pull-ups on porta register 2-2: option_reg ? option register (address: 81h) note: to achieve a 1:1 prescaler assignment for tmr0, assign the prescaler to the wdt by setting psa bit to ? 1 ? (option_reg<3>). see section 5.4 ?prescaler? . r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rapu intedg t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 bit 7 rapu : porta pull-up enable bit 1 = porta pull-ups are disabled 0 = porta pull-ups are enabled by individual port latch values in wpua register bit 6 intedg: interrupt edge select bit 1 = interrupt on rising edge of ra2/an2/t0cki/int/c1out pin 0 = interrupt on falling edge of ra2/an2/t0cki/int/c1out pin bit 5 t0cs: tmr0 clock source select bit 1 = transition on ra2/an2/t0cki/int/c1out pin 0 = internal instruction cycle clock (clkout) bit 4 t0se: tmr0 source edge select bit 1 = increment on high-to-low transition on ra2/an2/t0cki/int/c1out pin 0 = increment on low-to-high transition on ra2/an2/t0cki/int/c1out pin bit 3 psa: prescaler assignment bit 1 = prescaler is assigned to the wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps<2:0>: prescaler rate select bits note 1: a dedicated 16-bit wdt postscaler is available for the PIC16F785. see section 15.6 ?watchdog timer (wdt)? for more information. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value tmr0 rate wdt rate (1)
? 2004 microchip technology inc. preliminary ds41249a-page 17 PIC16F785 2.2.2.3 intcon register the intcon register is a readable and writable register, which contains the various enable and flag bits for tmr0 register overflow, porta change and external ra2/int pin interrupts. register 2-3: intcon ? interrupt control register (address: 0bh or 8bh) note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gie peie t0ie inte raie t0if intf raif bit 7 bit 0 bit 7 gie: global interrupt enable bit 1 = enables all unmasked interrupts 0 = disables all interrupts bit 6 peie: peripheral interrupt enable bit 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts bit 5 t0ie: tmr0 overflow interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4 inte: ra2/an2/t0cki/int/c1out external interrupt enable bit 1 = enables the ra2/an2/t0cki/int/c1out external interrupt 0 = disables the ra2/an2/t0cki/int/c1out external interrupt bit 3 raie: porta change interrupt enable bit (1) 1 = enables the porta change interrupt 0 = disables the porta change interrupt bit 2 t0if: tmr0 overflow interrupt flag bit (2) 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 intf: ra2/an2/t0cki/int/c1out external interrupt flag bit 1 = the ra2/an2/t0cki/int/c1out external inte rrupt occurred (must be cleared in software) 0 = the ra2/an2/t0cki/int/c1out external interrupt did not occur bit 0 raif: porta change interrupt flag bit 1 = when at least one of the porta <5:0> pins changed state (must be cleared in software) 0 = none of the porta <5:0> pins have changed state note 1: ioca register must also be enabled. 2: t0if bit is set when timer0 rolls over. timer0 is unchanged on reset and should be initialized before clearing t0if bit. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC16F785 ds41249a-page 18 preliminary ? 2004 microchip technology inc. 2.2.2.4 pie1 register the pie1 register contains the interrupt enable bits, as shown in register 2-4. register 2-4: pie1 ? peripheral interrupt enable register 1 (address: 8ch) note: bit peie (intcon<6>) must be set to enable any peripheral interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eeie adie ccp1ie c2ie c1ie osfie tmr2ie tmr1ie bit 7 bit 0 bit 7 eeie: ee write complete interrupt enable bit 1 = enables the ee write complete interrupt 0 = disables the ee write complete interrupt bit 6 adie: a/d converter interrupt enable bit 1 = enables the a/d converter interrupt 0 = disables the a/d converter interrupt bit 5 ccp1ie: ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 4 c2ie: comparator 2 interrupt enable bit 1 = enables the comparator 2 interrupt 0 = disables the comparator 2 interrupt bit 3 c1ie: comparator 1 interrupt enable bit 1 = enables the comparator 1 interrupt 0 = disables the comparator 1 interrupt bit 2 osfie: oscillator fail interrupt enable bit 1 = enables the oscillator fail interrupt 0 = disables the oscillator fail interrupt bit 1 tmr2ie: timer 2 to pr2 match interrupt enable bit 1 = enables the timer 2 to pr2 match interrupt 0 = disables the timer 2 to pr2 match interrupt bit 0 tmr1ie: timer 1 overflow interrupt enable bit 1 = enables the timer 1 overflow interrupt 0 = disables the timer 1 overflow interrupt legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds41249a-page 19 PIC16F785 2.2.2.5 pir1 register the pir1 register contains the interrupt flag bits, as shown in register 2-5. register 2-5: pir1 ? peripheral interrupt register 1 (address: 0ch) note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie (intcon<7>). user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eeif adif ccp1if c2if c1if osfif tmr2if tmr1if bit 7 bit 0 bit 7 eeif: eeprom write operation interrupt flag bit 1 = the write operation completed (must be cleared in software) 0 = the write operation has not completed or has not been started bit 6 adif: a/d interrupt flag bit 1 = a/d conversion complete 0 = a/d conversion has not completed or has not been started bit 5 ccp1if: ccp1 interrupt flag bit capture mod e: 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode : 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode : unused in this mode bit 4 c2if: comparator 2 interrupt flag bit 1 = comparator 2 output has changed (must be cleared in software) 0 = comparator 2 output has not changed bit 3 c1if: comparator 1 interrupt flag bit 1 = comparator 1 output has changed (must be cleared in software) 0 = comparator 1 output has not changed bit 2 osfif: oscillator fail interrupt flag bit 1 = system oscillator failed, clock input has changed to intosc (must be cleared in software) 0 = system clock operating bit 1 tmr2if: timer 2 to pr2 match interrupt flag bit 1 = timer 2 to pr2 match occurred (must be cleared in software) 0 = timer 2 to pr2 match has not occurred bit 0 tmr1if: timer 1 overflow interrupt flag bit 1 = timer 1 register overflowed (must be cleared in software) 0 = timer 1 has not overflowed legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC16F785 ds41249a-page 20 preliminary ? 2004 microchip technology inc. 2.2.2.6 pcon register the power control (pcon) register (see table 15-2) contains flag bits to differentiate between a: power-on reset (por ) brown-out reset (bor ) watchdog timer reset (wdt) external mclr reset the pcon register bits are shown in register 2-6. register 2-6: pcon ? power control register (address: 8eh) u-0 u-0 u-0 r/w-1 u-0 u-0 r/w-0 r/w-x ? ? ? sboren ? ?por bor bit 7 bit 0 bit 7-5 unimplemented: read as ? 0 ? bit 4 sboren: software bor enable bit (1) 1 = bor enabled 0 = bor disabled bit 3-2 unimplemented: read as ? 0 ? bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out resetoccurred (must be set in software after a brown-out reset occurs) note 1: boren<1:0> = 01 in configuration word for this bit to control the bor . legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds41249a-page 21 PIC16F785 2.3 pcl and pclath the program counter (pc) specifies the address of the instruction to fetch for execution. the program counter is 13 bits wide. the low byte is called the pcl register. the pcl register readable and writable. the high byte of the pc (pc<12:8>) is called the pch register. this register contains pc<12:8> bits which are not directly readable or writable. all updates to the pch register go through the pclath register. on any reset, the pc is cleared. figure 2-3 shows the two situations for the loading of the pc. the upper example in figure 2-3 shows how the pc is loaded on a write to pcl (pclath<4:0> pch). the lower example in figure 2-3 shows how the pc is loaded during a call or goto instruction (pclath<4:3> pch). 2.3.1 modifying pcl executing any instruction with the pcl register as the destination simultaneously causes the program counter pc<12:8> bits (pch) to be replaced by the contents of the pclath register. this allows the entire contents of the program counter to be changed by first writing the desired upper 5 bits to the pclath register. when the lower 8 bits are then written to the pcl register, all 13 bits of the program counter will change to the values contained in the pclath register and those being written to the pcl register. a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). care should be exercised when jumping into a look-up table or program branch table (computed goto ) by modifying the pcl register. assuming that pclath is set to the table start address, if the table length is greater than 255 instructions, or if the lower 8 bits of the memory address rolls over from 0xff to 0x00 in the middle of the table, then pclath must be incremented for each address rollover that occurs between the table beginning and the target location within the table. for more information refer to application note ds00556, ?implementing a table read? . 2.3.2 program memory paging the call and goto instructions provide 11 bits of address to allow branching within any 2k program memory page. when doing a call or goto instruction, the upper bit of the address is provided by pclath<3> (page select bit). when doing a call or goto instruc- tion the user must ensure that the page select bit is pro- grammed so that the desired destination program memory page is addressed. when the call instruction (or interrupt) is executed, the entire 13-bit pc return address is push ed onto the stack. therefore, manipu- lation of the pclath<3> bit is not required for the return or retfie instructions which pop the address from the stack. figure 2-3: loading of pc in different situations 2.3.3 stack the PIC16F785 family has an 8-level x 13-bit wide hardware stack (see figure 2-1). the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when a call instruction is executed or an interrupt causes a branch. the stack is poped in the event of a return, retlw or a retfie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer. this means that after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. the tenth push overwrites the second push (and so on). note 1: there are no status bits to indicate stack overflow or stack underflow conditions. 2: there are no instructions/mnemonics called push or pop . these are actions that occur from the execution of the call, return, retlw and retfie instruc- tions or the vectoring to an interrupt address. pc 12 8 7 0 5 pclath<4:0> pclath instruction with alu result goto, call opcode <10:0> 8 pc 12 11 10 0 11 pclath<4:3> pch pcl 87 2 pclath pch pcl pcl as destination
PIC16F785 ds41249a-page 22 preliminary ? 2004 microchip technology inc. 2.4 indirect addressing, indf and fsr registers the indf register is not a physical register. addressing the indf register will cause indirect addressing. indirect addressing is possible by using the indf register. any instruction using the indf register actually accesses data pointed to by the file select register (fsr). reading indf itself indirectly will produce 00h. writing to the indf register indirectly results in a no operation (although status bits may be affected). an effective 9-bit address is obtained by concatenating the 8-bit fsr and the irp bit (status<7>), as shown in figure 2-4. a simple program to clear ram location 20h ? 2fh using indirect addressing is shown in example 2-1. example 2-1: indirect addressing figure 2-4: direct/indirect addressing PIC16F785 movlw 0x20 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr ;increment pointer btfss fsr,4 ;all done? goto next ;no clear next continue ;yes continue for memory map detail see figure 2-2. data memory indirect addressing direct addressing bank select location select rp1 rp0 6 0 from opcode irp file select register 7 0 bank select location select 00 01 10 11 180h 1ffh 00h 7fh bank 0 bank 1 bank 2 bank 3
? 2004 microchip technology inc. preliminary ds41249a-page 23 PIC16F785 3.0 clock sources 3.1 overview the PIC16F785 has a wide variety of clock sources and selection features to allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. figure 3-1 illustrates a block diagram of the PIC16F785 clock sources. clock sources can be configured from external oscillators, quartz crystal resonators, ceramic resonators and resistor-capacitor (rc) circuits. in addition, the system clock source can be configured from one of two internal oscillators, with a choice of speeds selectable via software. additional clock features include: selectable system clock source between external or internal via software. two-speed clock start-up mode, which minimizes latency between external oscillator start-up and code execution. fail-safe clock monitor (fscm) designed to detect a failure of the external clock source (lp, xt, hs, ec or rc modes) and switch to the inter- nal oscillator. the PIC16F785 can be configured in one of eight clock modes. 1. ec - external clock with i/o on ra4. 2. lp - 32.768 khz watch crystal or ceramic resonator oscillator mode. 3. xt - medium gain crystal or ceramic resonator oscillator mode. 4. hs - high gain crystal or ceramic resonator mode. 5. rc - external resistor-capacitor (rc) with f osc /4 output on ra4 6. rcio - external resistor-capacitor with i/o on ra4. 7. intosc - internal oscillator with f osc /4 output on ra4 and i/o on ra5. 8. intoscio - internal oscillator with i/o on ra4 and ra5. clock source modes are configured by the fosc<2:0> bits in the configuration word (see section 15.0 ?special features of the cpu? ). once the PIC16F785 is programmed and the clock source mode configured, it cannot be changed in software. figure 3-1: PIC16F785 cl ock source block diagram (cpu and peripherals) osc1 osc2 sleep external oscillator lp, xt, hs, rc, rcio, ec system clock postscaler mux mux 8 mhz 4 mhz 2 mhz 1 mhz 500 khz 125 khz 250 khz ircf<2:0> 111 110 101 100 011 010 001 000 31 khz power-up timer (pwrt) fosc<2:0> (configuration word) scs (osccon<0>) internal oscillator (osccon<6:4>) watchdog timer (wdt) fail-safe clock monitor (fscm) hfintosc 8 mhz lfintosc 31 khz
PIC16F785 ds41249a-page 24 preliminary ? 2004 microchip technology inc. 3.2 clock source modes clock source modes can be classified as external or internal. external clock modes rely on external circuitry for the clock source. examples are oscillator modules (ec mode), quartz crystal resonators or ceramic resonators (lp, xt, and hs modes), and resistor-capacitor (rc mode) circuits. internal clock sources are contained internally within the PIC16F785. the PIC16F785 has two internal oscillators; the 8 mhz high-frequency internal oscillator (hfintosc) and 31 khz low-frequency internal oscillator (lfintosc). the system clock can be selected between external or internal clock sources via the system clock selection (scs) bit (see section 3.5 ?clock switching? ). 3.3 external clock modes 3.3.1 oscillator start-up timer (ost) when the PIC16F785 is configured for any of the crystal oscillator modes (lp, xt or hs), the oscillator start-up timer (ost) is enabled, which extends the reset period to allow the oscillator additional time to stabilize. the ost counts 1024 clock periods present on the osc1 pin following a power-on reset (por), a wake from sleep, or when the power-up timer (pwrt) has expired (if the pwrt is enabled). during this time, the program counter does not increment and program execution is suspended. the ost ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the PIC16F785. table 3-1 shows examples where the oscillator delay is invoked. in order to minimize latency between external oscillator start-up and code execution, the two-speed clock start-up mode can be selected (see section 3.6 ?two-speed clock start-up mode? ). table 3-1: oscillator delay examples 3.3.2 ec mode the external clock (ec) mode allows an externally generated logic level as the system clock source. when operating in this mode, an external clock source is connected to osc1 pin and the ra4 pin is available for general purpose i/o. figure 3-2 shows the pin connections for ec mode. the oscillator start-up timer (ost) is disabled when ec mode is selected. therefore, there is no delay in operation after a power-on reset (por) or wake-up from sleep. because the PIC16F785 design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. upon restarting the external clock, the device will resume operation as if no time had elapsed. figure 3-2: external clock (ec) mode operation switch from switch to frequency oscillator delay comments sleep/por intrc intosc 31 khz 125 khz?8 mhz 5 s?10 s (approx.) cpu start-up (1) following a wake-up from sleep mode or por, cpu start-up is invoked to allow the cpu to become ready for code execution. sleep ec, rc dc ? 20 mhz lfintosc (31 khz) ec, rc dc ? 20 mhz sleep/por lp, xt, hs 31 khz?20 mhz 1024 clock cycles (ost) lfintosc (31 khz) intosc 125 khz?8 mhz 1 s (approx.) note 1: the 5 s?10 s start-up delay is based on a 1 mhz system clock. osc1/clkin i/o (osc2) ra4 clock from ext. system PIC16F785
? 2004 microchip technology inc. preliminary ds41249a-page 25 PIC16F785 3.3.3 lp, xt, hs modes the lp, xt and hs modes support the use of quartz crystal resonators or ceramic resonators connected to the osc1 and osc2 pins (figure 3-1). the mode selects a low, medium, or high gain setting of the internal inverter-amplifier to support various resonator types and speed. lp oscillator mode selects the lowest gain setting of the internal inverter-amplifier. lp mode current consump- tion is the least of the three modes. this mode is best suited to drive resonators with a low drive level specifi- cation, for example, tuning fork type crystals. xt oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. xt mode current con- sumption is the medium of the three modes. this mode is best suited to drive resonators with a medium drive level specification, for example, at-cut quartz crystal resonators. hs oscillator mode selects the highest gain setting of the internal inverter-amplifier. hs mode current con- sumption is the highest of the three modes. this mode is best suited for resonators that require a high drive setting, for example, at-cut quartz crystal resonators or ceramic resonators. figure 3-3 and figure 3-4 show typical circuits for quartz crystal and ceramic resonators, respectively. figure 3-3: quartz crystal operation (lp, xt or hs mode) figure 3-4: ceramic resonator operation (xt or hs mode) note 1: quartz crystal characteristics vary according to type, package and manufac- turer. the user should consult the manu- facturer data sheets for specifications and recommended application. 2: always verify oscillator performance over the v dd and temperature range that is expected for the application. note 1: a series resistor (r s ) may be required for quartz crystals with low drive level. 2: the value of r f varies with the oscillator mode selected (typically between 2 m ? to 10 m ?) . c1 c2 quartz osc2 r s (1) osc1 r f (2) sleep to internal logic crystal PIC16F785 note 1: a series resistor (r s ) may be required for ceramic resonators with low drive level. 2: the value of r f varies with the oscillator mode selected (typically between 2 m ? to 10 m ?) . 3: an additional parallel feedback resistor (r p ) may be required for proper ceramic resonator operation (typical value 1 m ? ). c1 c2 ceramic osc2 r s (1) osc1 r f (2) sleep to internal logic r p (3) resonator PIC16F785
PIC16F785 ds41249a-page 26 preliminary ? 2004 microchip technology inc. 3.3.4 external rc modes the external resistor-capacitor (rc) modes support the use of an external rc circuit. this allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. there are two modes, rc and rcio. in rc mode, the rc circuit connects to the osc1 pin. the osc2/clkout pin outputs the rc oscillator frequency divided by 4. this signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. figure 3-5 shows the rc mode connections. figure 3-5: rc mode in rcio mode, the rc circuit is connected to the osc1 pin. the osc2 pin becomes an additional general purpose i/o pin. the i/o pin becomes bit 4 of porta (ra4). figure 3-6 shows the rcio mode connections. figure 3-6: rcio mode the rc oscillator frequency is a function of the supply voltage, the resistor (r ext ) and capacitor (c ext ) values and the operating temperature. in addition to this, the oscillator frequency will vary from unit-to-unit due to normal threshold voltage. furthermore, the dif- ference in lead frame capacitance between package types will also affect the oscillation frequency or low c ext values. the user also needs to take into account variation due to tolerance of external rc components used. 3.4 internal clock modes the PIC16F785 has two independent, internal oscillators that can be configured or selected as the system clock source. 1. the hfintosc (high-frequency internal oscillator) is factory calibrated and operates at 8 mhz. the frequency of the hfintosc can be user adjusted 12% via software using the osctune register (register 3-1). 2. the lfintosc (low-frequency internal oscillator) is uncalibrated and operates at approximately 31 khz. the system clock speed can be selected via software using the internal oscillator frequency select (ircf) bits. the system clock can be selected between external or internal clock sources via the system clock selection (scs) bit (see section 3.5 ?clock switching? ). 3.4.1 intrc and intrcio modes the intrc and intrcio modes configure the internal oscillators as the system clock source when the device is programmed using the oscillator selection (fosc) bits in the configuration word (register 12-1). in intrc mode, the osc1 pin is available for general purpose i/o. the osc2/clkout pin outputs the selected internal oscillator frequency divided by 4. the clkout signal may be used to provide a clock for external circuitry, synchronization, calibration, test or other application requirements. in intrcio mode, the osc1 and osc2 pins are avail- able for general purpose i/o. 3.4.2 hfintosc the high-frequency internal oscillator (hfintosc) is a factory calibrated 8 mhz internal clock source. the frequency of the hfintosc can be altered approximately 12% via software using the osctune register (register 3-1). the output of the hfintosc connects to a postscaler and multiplexer (see figure 3-1). one of seven frequencies can be selected via software using the ircf bits (see section 3.4.4 ?frequency select bits (ircf)? ). the hfintosc is enabled by selecting any frequency between 8 mhz and 125 khz (ircf 000 ) as the sys- tem clock source (scs = 1 ) or when two-speed start-up is enabled (ieso = 1 and ircf 000 ). the hf internal oscillator (hts) bit, (osccon<2>), indicates whether the hfintosc is stable or not. osc2/clkout c ext r ext osc1 f osc /4 internal clock v dd v ss recommended values: 3 k ? r ext 100 k ? (v dd 3v) 10 k ? r ext 100 k ? (v dd < 3v) c ext > 20 pf PIC16F785 c ext r ext osc1 internal clock v dd v ss i/o (osc2) ra4 PIC16F785 recommended values: 3 k ? r ext 100 k ? (v dd 3v) 10 k ? r ext 100 k ? (v dd < 3v) c ext > 20 pf
? 2004 microchip technology inc. preliminary ds41249a-page 27 PIC16F785 3.4.2.1 calibration bits the 8 mhz high-frequency internal oscillator (hfintosc) is factory calibrated. the hfintosc calibration bits are stored in the calibration word (calib) located in program memory location 2008h. the calibration word is not erased using the specified bulk erase sequence in the PIC16F785 memory programming specification (ds41237) and does not require reprogramming. for more information on the calibration word register (see section 15.2 ?calibration bits? ). 3.4.2.2 osctune register the hfintosc is factory calibrated but can be adjusted in software by writing to the osctune register (register 3-1). the osctune register has a tuning range of 12%. the default value of the osctune register is ? 0 ?. the value is a 5-bit two's complement number. due to process variation, the monotonicity and frequency step cannot be specified. when the osctune register is modified, the hfintosc frequency will begin shifting to the new frequency. the hfintosc clock will stabilize within 1 ms. code execution continues during this shift. there is no indication that the shift has occurred. osctune does not affect the lfintosc frequency. operation of features that depend on the lfintosc clock source frequency, such as the power-up timer (pwrt), watchdog timer (wdt), fail-safe clock monitor (fscm) and peripherals, are not affected by the change in frequency. register 3-1: osctune ? oscillator tuning resistor (address 90h) note: address 2008h is beyond the user program memory space. it belongs to the special configuration memory space (2000h ? 3fffh), which can be accessed only during programming. see PIC16F785 memory programming specification (ds41237) for more information. u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? tun4 tun3 tun2 tun1 tun0 bit 7 bit 0 bit 7-5 unimplemented: read as ? 0 ? bit 4-0 tun<4:0>: frequency tuning bits 01111 = maximum frequency 01110 = 00001 = 00000 = center frequency. oscillator module is running at the calibrated frequency. 11111 = 10000 = minimum frequency legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC16F785 ds41249a-page 28 preliminary ? 2004 microchip technology inc. 3.4.3 lfintosc the low-frequency internal oscillator (lfintosc) is an uncalibrated (approximate) 31 khz internal clock source. the output of the lfintosc connects to a postscaler and multiplexer (see figure 3-1). 31 khz can be selected via software using the ircf bits (see section 3.4.4 ?frequency select bits (ircf)? ). the lfintosc is also the frequency for the power-up timer (pwrt), watchdog timer (wdt) and fail-safe clock monitor (fscm). the lfintosc is enabled by selecting 31 khz (ircf = 000 ) as the system clock source (scs = 1 ), or when any of the following are enabled: two-speed start-up (ieso = 1 and ircf = 000 ) power-up timer (pwrt) watchdog timer (wdt) fail-safe clock monitor (fscm) the lf internal oscillator (lts) bit, (osccon<1>), indicates whether the lfintosc is stable or not. 3.4.4 frequency select bits (ircf) the output of the 8 mhz hfintosc and 31 khz lfintosc connect to a postscaler and multiplexer (see figure 3-1). the internal oscillator frequency select bits ircf<2:0> (osccon<6:4>) select the frequency output of the internal oscillators. one of eight frequencies can be selected via software: 8 mhz 4 mhz (default after reset) 2 mhz 1 mhz 500 khz 250 khz 125 khz 31 khz 3.4.5 hf and lf intosc clock switch timing when switching between the lfintosc and the hfintosc, the new oscillator may already be shut down to save power. if this is the case, there is a 10 s delay after the ircf bits are modified before the frequency selection takes place. the lts/hts bits will reflect the current active status of the lfintosc and the hfintosc oscillators. the timing of a frequency selection is as follows: 1. ircf bits are modified. 2. if the new clock is shut down, a 10 s clock start-up delay is started. 3. clock switch circuitry waits for a falling edge of the current clock. 4. clkout is held low and the clock switch circuitry waits for a rising edge in the new clock. 5. clkout is now connected with the new clock. hts/lts bits are updated as required. 6. clock switch is complete. if the internal oscillator speed selected is between 8 mhz and 125 khz, there is no start-up delay before the new frequency is selected. this is because the old and the new frequencies are derived from the hfintosc via the postscaler and multiplexer. note: following any reset, the ircf bits are set to ? 110 ? and the frequency selection is forced to 4 mhz. the user can modify the ircf bits to select a different frequency. note: care must be taken to ensure an invalid voltage or frequency selection is not selected. an example of an invalid config- uration is selecting 8 mhz when v dd is 2.0v.
? 2004 microchip technology inc. preliminary ds41249a-page 29 PIC16F785 3.5 clock switching the system clock source can be switched between external and internal clock sources via software using the system clock select (scs) bit. 3.5.1 system clock select (scs) bit the system clock select (scs) bit, (osccon<0>), selects the system clock source that is used for the cpu and peripherals. when scs = 0 , the system clock source is determined by configuration of the fosc<2:0> bits in configuration word (config). when scs = 1 , the system clock source is chosen by the internal oscillator frequency selected by the ircf bits. after a reset, scs is always cleared. 3.5.2 oscillator start-up time-out status bit the oscillator start-up time-out status (osts) bit, (osccon<3>), indicates whether the system clock is running from the external clock source as defined by the fosc bits, or from internal clock source. in particular, osts indicates that the oscillator start-up timer (ost) has timed out for lp, xt or hs modes. 3.6 two-speed clock start-up mode two-speed start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. in applications that make heavy use of the sleep mode, two-speed start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. this mode allows the application to wake-up from sleep, perform a few instructions using the intosc as the clock source and go back to sleep without wait- ing for the primary oscillator to become stable. when the PIC16F785 is configured for lp, xt, or hs modes, the oscillator start-up timer (ost) is enabled (see section 3.3.1 ?oscillator start-up timer (ost)? ). the ost timer will suspend program execu- tion until 1024 oscillations are counted. two-speed start-up mode minimizes the delay in code execution by operating from the internal oscillator as the ost is counting. when the ost count reaches 1024 and the osts bit (osccon<3>) is set, program execution switches to the external oscillator. 3.6.1 two-speed start-up mode configuration two-speed start-up mode is configured by the following settings: ieso = 1 (config<10>) internal/external switch over bit. scs = 0 . f osc configured for lp, xt or hs mode. two-speed start-up mode is entered after: power-on reset (por) and, if enabled, after pwrt has expired, or wake-up from sleep. if the external clock oscillator is configured to be any- thing other than lp, xt or hs mode, then two-speed start-up is disabled. this is because the external clock oscillator does not require any stabilization time after por or an exit from sleep. 3.6.2 two-speed start-up sequence 1. wake-up from power-on reset or sleep. 2. instructions begin execution by the internal oscillator at the frequency set in the ircf bits (osccon<6:4>). 3. ost enabled to count 1024 clock cycles. 4. ost timed out, wait for falling edge of the internal oscillator. 5. osts is set. 6. system clock held low until the next falling edge of new clock (lp, xt or hs mode). 7. system clock is switched to external clock source. 3.6.3 checking external/internal clock status checking the state of the osts bit (osccon<3>) will confirm if the PIC16F785 is running from the external clock source as defined by the f osc bits in the configuration word (config) or the internal oscillator. note: any automatic clock switch, which may occur from two-speed start-up or fail-safe clock monitor, does not update the scs bit. the user can monitor the osts (osccon<3>) to determine the current system clock source. note: executing a sleep instruction will abort the oscillator start-up time and will cause the osts bit (osccon<3>) to remain clear.
PIC16F785 ds41249a-page 30 preliminary ? 2004 microchip technology inc. figure 3-7: two-speed start-up 3.7 fail-safe clock monitor the fail-safe clock monitor (fscm) is designed to allow the device to continue to operate in the event of an oscillator failure. the fscm can detect oscillator failure at any point after the device has exited a reset or sleep condition and the oscillator start-up timer (ost) has expired. figure 3-8: fscm block diagram the fscm function is enabled by setting the fcmen bit in configuration word (config). it is applicable to all external clock options (lp, xt, hs, ec, rc or i/o modes). in the event of an external clock failure, the fscm will set the osfif bit (pir1<2>) and generate an oscillator fail interrupt if the osfie bit (pie1<2>) is set. the device will then switch the system clock to the internal oscillator. the system clock will continue to come from the internal oscillator unless the external clock recovers and the fail-safe condition is exited. the frequency of the internal oscillator will depend upon the value contained in the ircf bits (osccon<6:4>). upon entering the fail-safe condition, the osts bit (osccon<3>) is automatically cleared to reflect that the internal oscillator is active and the wdt is cleared. the scs bit (osccon<0>) is not updated. enabling fscm does not affect the lts bit. the fscm sample clock is generated by dividing the lfintosc clock by 64. this will allow enough time between fscm sample clocks for a system clock edge to occur. figure 3-8 shows the fscm block diagram. on the rising edge of the sample clock, the monitoring latch (cm = 0 ) will be cleared. on a falling edge of the primary system clock, the monitoring latch will be set (cm = 1 ). in the event that a falling edge of the sample clock occurs, and the monitoring latch is not set, a clock failure has been detected. the assigned internal oscillator is enabled when fscm is enabled as reflected by the ircf bits. q1 q2 q3 q4 q1 q2 q3 q4 q1 0 1 1022 1023 pc pc + 1 pc + 2 t ost t intosc osc1 osc2 program counter system clock primary lfintosc 64 s c q 31 khz (~32 s) 488 hz (~2 ms) clock monitor latch (cm) (edge-triggered) clock failure detected oscillator clock q note: two-speed start-up is automatically enabled when the fail-safe clock monitor mode is enabled.
? 2004 microchip technology inc. preliminary ds41249a-page 31 PIC16F785 3.7.1 fail-safe condition clearing the fail-safe condition is cleared after a reset, the execution of a sleep instruction, or a modification of the scs bit. while in fail-safe condition, the PIC16F785 uses the internal oscillator as the system clock source. the ircf bits (osccon<6:4>) can be modified to adjust the internal oscillator frequency without exiting the fail-safe condition. the fail-safe condition must be cleared before the osfif flag can be cleared. figure 3-9: fscm timing diagram 3.7.2 reset or wake-up from sleep the fscm is designed to detect oscillator failure at any point after the device has exited a reset or sleep condition and the oscillator start-up timer (ost) has expired. if the external clock is ec or rc mode, monitoring will begin immediately following these events. for lp, xt or hs mode, the external oscillator may require a start-up time considerably longer than the fscm sample clock time; a false clock failure may be detected (see figure 3-9). to prevent this, the internal oscillator is automatically configured as the system clock and functions until the external clock is stable (the ost has timed out). this is identical to two-speed start-up mode. once the external oscilla- tor is stable, the lfintosc returns to its role as the fscm source. oscfif cm output system clock output sample clock failure detected oscillator failure note: the system clock is normally at a much higher frequency than the sample clock. the relative frequencies in this example have been chosen for clarity. (q ) cm test cm test cm test note: due to the wide range of oscillator start-up times, the fail-safe circuit is not active during oscillator start-up (i.e., after exiting reset or sleep). after an appropriate amount of time, the user should check the osts bit (osccon<3>) to verify the oscillator start-up and system clock switchover has successfully completed.
PIC16F785 ds41249a-page 32 preliminary ? 2004 microchip technology inc. register 3-2: osccon ? oscillator control register (address: 8fh) table 3-2: summary of registers associated with clock sources u-0 r/w-1 r/w-1 r/w-0 r-q r-0 r-0 r/w-0 ? ircf2 ircf1 ircf0 osts (1) hts lts scs bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6-4 ircf<2:0>: internal oscillator frequency select bits 000 =31khz 001 = 125 khz 010 = 250 khz 011 = 500 khz 100 =1mhz 101 =2mhz 110 =4mhz 111 =8mhz bit 3 osts: oscillator start-up time-out status bit 1 = device is running from the external system clock defined by fosc<2:0> 0 = device is running from the internal system clock (hfintosc or lfintosc) bit 2 hts: hfintosc (high frequency - 8 mhz to 125 khz) status bit 1 =hfintosc is stable 0 = hfintosc is not stable bit 1 lts: lfintosc (low frequency - 31 khz) stable bit 1 = lfintosc is stable 0 = lfintosc is not stable bit 0 scs: system clock select bit 1 = internal oscillator is used for system clock 0 = clock source defined by fosc<2:0> note 1: bit resets to ? 0 ? with two-speed start-up and lp, xt or hs selected as the oscillator mode or fail-safe mode is enabled, otherwise this bit resets to ? 1 ?. legend: q = value depends on condition r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0ch pir1 eeif adif ccp1if c2if c1if osfif tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 eeie adie ccp1ie c2ie c1ie osfie tmr2ie tmr1ie 0000 0000 0000 0000 8fh osccon ? ircf2 ircf1 ircf0 osts hts lts scs -110 q000 -110 q000 90h osctune ? ? ? tun4 tun3 tun2 tun1 tun0 ---0 0000 ---u uuuu 2007h (1) config cpd cp mclre pwrte wdte fosc2 fosc1 fosc0 ? ? legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?, q= value depends on condition. shaded cells are not used by oscillators. note 1: see register 15-1 for operation of all configuration word bits.
? 2004 microchip technology inc. preliminary ds41249a-page 33 PIC16F785 4.0 i/o ports there are seventeen general purpose i/o pins and one input only pin available. depending on which peripher- als are enabled, some or all of the pins may not be available as general purpose i/o. in general, when a peripheral is enabled, the associated pin may not be used as a general purpose i/o pin. 4.1 porta and trisa registers porta is a 6-bit wide, bidirectional port. the corresponding data direction register is trisa (register 4-2). setting a trisa bit (= 1 ) will make the corresponding porta pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisa bit (= 0 ) will make the corresponding porta pin an output (i.e., put the contents of the output latch on the selected pin). the exception is ra3, which is input only and its tris bit will always read as ? 1 ?. example 4-1 shows how to initialize porta. reading the porta register (register 4-1) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read; this value is modified and then writ- ten to the port data latch. ra3 reads ? 0 ? when mclre = 1 . the trisa register controls the direction of the porta pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. i/o pins configured as analog inputs always read ? 0 ?. when ra1 is configured as a voltage reference output, the ra1 digital output driver will automatically be dis- abled while not affecting the trisa<1> value. example 4-1: initializing porta register 4-1: porta ? porta register (address: 05h, 105h) note: additional information on i/o ports may be found in the picmicro ? mid-range reference manual (ds33023). note: the ansel0 (91h) register must be initial- ized to configure an analog channel as a digital input. pins configured as analog inputs will read ? 0 ?. bcf status,rp0 ;bank 0 bcf status,rp1 ; clrf porta ;init porta movlw f8h ;set ra<2:0> to andwf ansel0,f ; digital i/o bsf status,rp0 ;bank 1 movlw 0ch ;set ra<3:2> as inputs movwf trisa ; and set ra<5:4,1:0> ; as outputs bcf status,rp0 ;bank 0 u-0 u-0 r/w-x r/w-x (1) r/w-x r/w-x (1) r/w-x (1) r/w-x (1) ? ? ra5 ra4 ra3 ra2 ra1 ra0 bit 7 bit 0 bit 7-6: unimplemented : read as ? 0 ? bit 5-0: ra<5:0> : porta i/o pin 1 = port pin is >v ih 0 = port pin is PIC16F785 ds41249a-page 34 preliminary ? 2004 microchip technology inc. register 4-2: trisa ? porta tristate register (address: 85h, 185h) 4.2 additional pin functions every porta pin on the PIC16F785 has an interrupt- on-change option and a weak pull-up option. the next three sections describe these functions. 4.2.1 weak pull-ups each of the porta pins has an individually config- urable internal weak pull-up. control bits wpuax enable or disable each pull-up. refer to register 4-3. each weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are dis- abled on a power-on reset by the rapu bit (option_reg<7>). the weak pull-up on ra3 is auto- matically enabled when ra3 is configured as mclr . register 4-3: wpua ? weak pull-up register (address: 95h) (1,2) u-0 u-0 r/w-1 r/w-1 r-1 r/w-1 r/w-1 r/w-1 ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 bit 7 bit 0 bit 7-6: unimplemented: read as ? 0 ? bit 5-0: trisa<5:0>: porta tri-state control bit (1)(2) 1 = porta pin configured as an input (tri-stated) 0 = porta pin configured as an output note 1: trisa<3> always reads ? 1 ?. 2: trisa<5:4> always reads ? 1 ? in xt, hs and lp osc modes. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por 1 = bit is set 0 = bit is cleared x = bit is unknown u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? wpua5 (4) wpua4 (4) wpua3 (3) wpua2 wpua1 wpua0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-0 wpua<5:0>: weak pull-up register bits 1 = pull-up enabled 0 = pull-up disabled note 1: global rapu must be enabled for individual pull-ups to be enabled. 2: the weak pull-up device is automatically disabled if the pin is in output mode (trisa = 0 ). 3: the ra3 pull-up is automatically enabled when configured as mclr in the configuration word. 4: wpua<5:4> always reads ? 1 ? in xt, hs and lp osc modes. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds41249a-page 35 PIC16F785 4.2.2 interrupt-on-change each of the porta pins is individually configurable as an interrupt-on-change pin. control bits iocax enable or disable the interrupt function for each pin. refer to register 4-4. the interrupt-on-change is disabled on a power-on reset. for enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of porta. the ?mismatch? outputs of the last read are or'd together to set, the porta change interrupt flag bit (raif) in the intcon register (register 2-3). this interrupt can wake the device from sleep. the user, in the interrupt service routine, clears the interrupt by: a) any read or write of porta. this will end the mismatch condition, then, b) clear the flag bit raif. a mismatch condition will continue to set flag bit raif. reading porta will end the mismatch condition and allow flag bit raif to be cleared. the latch holding the last read value is neither affected by an mclr nor bor reset. after these resets, the raif flag will continue to be set if a mismatch is present. register 4-4: ioca ? interrupt-on-change porta register (address: 96h) (1) note: if a change on the i/o pin should occur when the read operation is being executed (start of the q2 cycle), then the raif interrupt flag may not get set. u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ioca5 ioca4 ioca3 ioca2 ioca1 ioca0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ? bit 5-0 ioca<5:0>: interrupt-on-change porta control bits (2) 1 = interrupt-on-change enabled 0 = interrupt-on-change disabled note 1: global interrupt enable (gie) must be enabled for individual interrupts to be recognized. 2: ioca<5:4> always reads ? 1 ? in xt, hs and lp osc modes. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC16F785 ds41249a-page 36 preliminary ? 2004 microchip technology inc. 4.2.3 porta pin descriptions and diagrams each porta pin is multiplexed with other functions. the pins and their combined functions are briefly described here. for specific information about individ- ual functions such as the comparator or the a/d, refer to the appropriate section in this data sheet. 4.2.3.1 ra0/an0/c1in+/icspdat figure 4-1 shows the diagram for this pin. the ra0 pin is configurable to function as one of the following: a general purpose i/o an analog input for the a/d an analog input to comparator 1 in-circuit serial programming ? data figure 4-1: block diagram of ra0 4.2.3.2 ra1/an1/c12in0-/v ref /icspclk figure 4-1 shows the diagram for this pin. the ra1 pin is configurable to function as one of the following: a general purpose i/o an analog input for the a/d an analog input to comparators 1 & 2 a voltage reference input for the a/d a buffered or unbuffered voltage reference output in-circuit serial programming clock figure 4-2: block diagram of ra1 i/o pin v dd v ss d q ck q d q ck q d q ck q d q ck q v dd weak data bus wr wpua rd wpua rd porta rd porta wr porta wr trisa rd trisa wr ioca rd ioca interrupt-on- to comparator to a/d converter ans0 rapu change ans0 d en q d en q d en q q1 q3 i/o pin v dd v ss d q ck q d q ck q d q ck q d q ck q v dd weak data bus wr wpua rd wpua rd porta wr porta wr trisa rd trisa wr ioca rd ioca interrupt-on- to comparators to a/d converter rapu change ans1 cvroe vroe*vren vr out rd porta d en q d en q d en q q1 q3
? 2004 microchip technology inc. preliminary ds41249a-page 37 PIC16F785 4.2.3.3 ra2/an2/t0cki/int/c1out figure 4-3 shows the diagram for this pin. the ra2 pin is configurable to function as one of the following: a general purpose i/o an analog input for the a/d the clock input for tmr0 an external edge triggered interrupt a digital output from comparator 1 figure 4-3: block diagram of ra2 4.2.3.4 ra3/mclr /v pp figure 4-4 shows the diagram for this pin. the ra3 pin is configurable to function as one of the following: a general purpose input as master clear reset w/weak pull-up figure 4-4: block diagram of ra3 i/o pin v dd v ss d q ck q d q ck q d q ck q d q ck q v dd weak ans2 data bus wr wpua rd wpua rd porta wr porta wr trisa rd trisa wr ioca rd ioca to a/d converter 0 1 to i n t to t m r 0 ans2 rapu interrupt-on- change c1out c1oe d en q d en q d en q q1 q3 rd porta input v ss d q ck q rd porta wr ioca rd ioca reset mclre rd trisa v ss mclre v dd weak mclre interrupt-on- change pin d en q d en q d en q q1 q3 rd porta d q ck q data bus wr wpua rd wpua r apu
PIC16F785 ds41249a-page 38 preliminary ? 2004 microchip technology inc. 4.2.3.5 ra4/an3/t1g/osc2/clkout figure 4-5 shows the diagram for this pin. the ra4 pin is configurable to function as one of the following: a general purpose i/o an analog input for the a/d a tmr1 gate input a crystal/resonator connection a clock output figure 4-5: block diagram of ra4 4.2.3.6 ra5/t1cki/osc1/clkin figure 4-6 shows the diagram for this pin. the ra5 pin is configurable to function as one of the following: a general purpose i/o a tmr1 clock input a crystal/resonator connection a clock input figure 4-6: block diagram of ra5 i/o pin v dd v ss d q ck q d q ck q d q ck q d q ck q v dd weak data bus wr wpua rd wpua rd porta wr porta wr trisa rd trisa wr ioca rd ioca f osc /4 to a/d converter oscillator circuit osc1 clkout 0 1 enable ans3 rapu to t 1 g intosc/ rc/ec (2) clk (1) modes clkout enable note 1: clk modes are xt, hs, lp, lptmr1 and clkout enable. 2: with clkout option. interrupt-on- change ans3 d en q d en q d en q q1 q3 rd porta s i/o pin v dd v ss d q ck q d q ck q d q ck q d q ck q v dd weak data bus wr wpua rd wpua rd porta wr porta wr trisa rd trisa wr ioca rd ioca to tmr1 or clkgen intosc mode intosc mode rapu osc2 (2) note 1: clk modes are xt, hs, lp and lptmr1. 2: when using timer1 with lp oscillator, the schmitt trigger is bypassed. clk modes (1) interrupt-on- change oscillator circuit d en q d en q d en q q1 q3 rd porta s
? 2004 microchip technology inc. preliminary ds41249a-page 39 PIC16F785 table 4-1: summary of registers associated with porta addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 05h, 105h porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --xx xxxx --uu uuuu 10h t1con t1ginv tmr1ge t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 0000 0000 0bh, 8bh intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 81h, 181h option_reg rapu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 85h, 185h trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 91h ansel0 ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 1111 1111 1111 1111 95h wpua ? ? wpua5 wpua4 wpua3 wpua2 wpua1 wpua0 --11 1111 --11 1111 96h ioca ? ? ioca5 ioca4 ioca3 ioca2 ioca1 ioca0 --00 0000 --00 0000 98h refcon ? ? bgst vrbb vren vroe cvroe ? --00 000- --00 000- 119h cm1con0 c1on c1out c1oe c1pol c1sp c1r c1ch1 c1ch0 0000 0000 0000 0000 11bh cm2con1 mc1out mc2out ? ? ? ?t1gss c2sync 00-- --10 00-- --10 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by porta.
PIC16F785 ds41249a-page 40 preliminary ? 2004 microchip technology inc. 4.3 portb and trisb registers portb is a 4-bit wide, bidirectional port. the corresponding data direction register is trisb (register 4-6). setting a trisb bit (= 1 ) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisb bit (= 0 ) will make the corresponding portb pin an output (i.e., put the contents of the output latch on the selected pin). example 4-2 shows how to initialize portb. reading the portb register (register 4-5) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then writ- ten to the port data latch. pin rb6 is an open drain output. all other portb pins have full cmos output drivers. the trisb register controls the direction of the portb pins, even when they are being used as analog inputs. the user must ensure the bits in the trisb register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ?. example 4-2: initializing portb register 4-5: portb ? portb register (address: 06h, 106h) register 4-6: trisb ? portb tristate register (address: 86h, 186h) note: the ansel1 (93h) register must be initial- ized to configure an analog channel as a digital input. pins configured as analog inputs will read ? 0 ?. bcf status,rp0 ;bank 0 bcf status,rp1 ; clrf portb ;init portb bsf status,rp0 ;bank 1 bcf ansel1,2 ;digital i/o - rb4 bcf ansel1,3 ;digital i/o - rb5 movlw 30h ;set rb<5:4> as inputs movwf trisb ;and set rb<7:6> ;as outputs bcf status,rp0 ;bank 0 r/w-x r/w-x r/w-x (1) r/w-x (1) u-0 u-0 u-0 u-0 rb7 rb6 rb5 rb4 ? ? ? ? bit 7 bit 0 bit 7-4: rb<7:4>: portb general purpose i/o pin bits 1 = port pin is > v ih 0 = port pin is < v il bit 3-0: unimplemented: read as ? 0 ? note 1: data latches are unknown after a por, but each port bit reads ?0? when the corre- sponding analog select bit is ?1? (see register 12-2 on page 80). legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown r/w-1 r/w-1 r/w-1 r/w-1 u-0 u-0 u-0 u-0 trisb7 trisb6 trisb5 trisb4 ? ? ? ? bit 7 bit 0 bit 7-4: trisb<7:4>: portb tri-state control bits 1 = portb pin configured as an input (tri-stated) 0 = portb pin configured as an output bit 3-0 unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds41249a-page 41 PIC16F785 4.3.1 portb pin descriptions and diagrams each portb pin is multiplexed with other functions. the pins and their combined functions are briefly described here. for specific information about individ- ual functions such as the pwm, operational amplifier, or the a/d, refer to the appropriate section in this data sheet. 4.3.1.1 rb4/an10/op2- the rb4/an10/op2- pin is configurable to function as one of the following: a general purpose i/o an analog input to the a/d an analog input to op amp 2 4.3.1.2 rb5/an11/op2+ the rb5/an11/op2+ pin is configurable to function as one of the following: a general purpose i/o an analog input to the a/d an analog input to op amp 2 figure 4-7: block diagram of rb4 and rb5 4.3.1.3 rb6 the rb6 pin is configurable to function as the following: an open drain general purpose i/o figure 4-8: block diagram of rb6 4.3.1.4 rb7/sync the rb7/sync pin is configurable to function as one of the following: a general purpose i/o pwm synchronization input and output figure 4-9: block diagram of rb7 i/o pin v dd v ss d q ck q d q ck q data bus wr portb wr trisb rd trisb to a/d converter rd portb ans10 (rb4) ans11 (rb5) to op amp2 d en q i/o pin v ss d q ck q d q ck q data bus wr portb wr trisb rd trisb n v ss rd portb d en q i/o pin v dd v ss d q ck q d q ck q data bus wr portb wr trisb rd trisb 0 1 sync out pwm master to pwm sync input ph1en ph2en rd portb d en q
PIC16F785 ds41249a-page 42 preliminary ? 2004 microchip technology inc. table 4-2: summary of registers associated with portb address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 06h, 106h portb rb7 rb6 rb5 rb4 ? ? ? ? xxxx ---- uuuu ---- 86h, 186h trisb trisb7 trisb6 trisb5 trisb4 ? ? ? ? 1111 ---- 1111 ---- 93h ansel1 ? ? ? ? ans11 ans10 ans9 ans8 ---- 1111 ---- 1111 111h pwmcon0 prsen pasen blank2 blank1 sync1 sync0 ph2en ph1en 0000 0000 0000 0000 11dh opa2con opaon ? ? ? ? ? ? ? 0--- ---- 0--- ---- legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by portb.
? 2004 microchip technology inc. preliminary ds41249a-page 43 PIC16F785 4.4 portc and trisc registers portc is an 8-bit wide, bidirectional port. the corre- sponding data direction register is trisc (register 4-8). setting a trisc bit (= 1 ) will make the corresponding portc pin an input (i.e., put the corre- sponding output driver in a high-impedance mode). clearing a trisc bit (= 0 ) will make the corresponding portc pin an output (i.e., put the contents of the out- put latch on the selected pin). example 4-3 shows how to initialize portc. reading the portc register (register 4-7) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch. the trisc register controls the direction of the portc pins, even when they are being used as analog inputs. the user must ensure the bits in the trisc register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ? . when rc4 or rc5 is configured as an op amp output, the corresponding rc4 or rc5 digital output driver will automatically be disabled regardless of the trisc<4> or trisc<5> value. example 4-3: initializing portc register 4-7: portc ? portc register (address: 07h, 107h) register 4-8: trisc ? portc tristate register (address: 87h, 187h) note: the ansel0 (91h) and ansel1 (93h) registers must be initialized to configure an analog channel as a digital input. pins configured as analog inputs will read ? 0 ?. bcf status,rp0 ;bank 0 bcf status,rp1 clrf portc ;init portc bsf status,rp0 ;bank 1 clrf ansel0 ;digital i/o clrf ansel1 ;digital i/o movlw 0ch ;set rc<3:2> as inputs movwf trisc ; and set rc<5:4,1:0> ; as outputs bcf status,rp0 ;bank 0 r/w-x (1) r/w-x (1) r/w-x r/w-x r/w-x (1) r/w-x (1) r/w-x (1) r/w-x (1) rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 bit 7 bit 0 bit 7-0: rc<7:0>: portc general purpose i/o pin bits 1 = port pin is greater than v ih 0 = port pin is less than v il note 1: data latches are unknown after a por, but each port bit reads ? 0 ? when the corre- sponding analog select bit is ? 1 ? (see register 12-1 and register 12-2 on page 80). legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 bit 7 bit 0 bit 7-0: trisc<7:0>: portc tri-state control bits 1 = portc pin configured as an input (tri-stated) 0 = portc pin configured as an output legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC16F785 ds41249a-page 44 preliminary ? 2004 microchip technology inc. 4.4.1 portc pin descriptions and diagrams each portc pin is multiplexed with other functions. the pins and their combined functions are briefly described here. for specific information about individ- ual functions such as the comparator or the a/d, refer to the appropriate section in this data sheet. 4.4.1.1 rc0/an4/c2in+ the rc0 is configurable to function as one of the following: a general purpose i/o an analog input for the a/d converter the non-inverting input to comparator 2 4.4.1.2 rc6/an8/op1- the rc6/an8/op1- pin is configurable to function as one of the following: a general purpose i/o an analog input for the a/d the inverting input for op amp 1 4.4.1.3 rc7/an9/op1+ the rc7/an9/op1+ pin is configurable to function as one of the following: a general purpose i/o an analog input for the a/d the non-inverting input for op amp 1 figure 4-10: block diagram of rc0, rc6 and rc7 4.4.1.4 rc1/an5/c12in1-/ph1 the rc1 is configurable to function as one of the following: a general purpose i/o an analog input for the a/d converter an analog input to comparators 1 & 2 a digital output from the two-phase pwm figure 4-11: block diagram of rc1 i/o pin v dd v ss d q ck q d q ck q data bus wr portc wr trisc rd trisc to a/d converter ans4 (rc0) ans8 (rc6) to comparators (rc0) to op amp1 (rc6, rc7) rd portc d en q ans9 (rc7) i/o pin v dd v ss d q ck q d q ck q data bus wr portc wr trisc rd trisc to a/d converter ans5 to comparators 0 1 ph1 ph1en rd portc d en q
? 2004 microchip technology inc. preliminary ds41249a-page 45 PIC16F785 4.4.1.5 rc2/an6/c12in2-/op2 the rc2 is configurable to function as one of the following: a general purpose i/o an analog input for the a/d converter an analog input to comparators 1 & 2 an analog output from op amp 2 4.4.1.6 rc3/an7/c12in3-/op1 the rc3 is configurable to function as one of the following: a general purpose i/o an analog input for the a/d converter an analog input to comparators 1 & 2 an analog output for op amp 1 figure 4-12: block diagram of rc2 and rc3 4.4.1.7 rc4/c2out/ph2 the rc4 is configurable to function as one of the following: a general purpose i/o a digital output from comparator 2 a digital output from the two-phase pwm figure 4-13: block diagram of rc4 i/o pin v dd v ss d q ck q d q ck q data bus wr portc wr trisc rd trisc to a/d converter ans6 (rc2) ans7 (rc3) to comparators opamp out opaon rd portc d en q i/o pin v dd v ss d q ck q d q ck q data bus wr portc wr trisc rd trisc 0 1 ph2 0 1 c2out ph2en c2oe rd portc d en q
PIC16F785 ds41249a-page 46 preliminary ? 2004 microchip technology inc. 4.4.1.8 rc5/ccp1 the rc5 is configurable to function as one of the following: a general purpose i/o a digital input for the capture/compare a digital output for the ccp figure 4-14: block diagram of rc5 pin table 4-3: summary of registers associated with portc i/o pin v dd v ss d q ck q d q ck q data bus wr portc wr trisc rd trisc 0 1 ccp out ccp1con<3> ccp1con<1> to ccp capture input rd portc d en q ccp1con<2> address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 07h, 107h portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu 15h ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 0000 0000 87h, 187h trisc trisc7 trisc6 trisc 5trisc4trisc3trisc2trisc1trisc0 1111 1111 1111 1111 91h ansel0 ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 1111 1111 1111 1111 93h ansel1 ? ? ? ? ans11 ans10 ans9 ans8 ---- 1111 ---- 1111 111h pwmcon0 prsen pasen blank2 blank1 sync1 sync0 ph2en ph1en 0000 0000 0000 0000 11ch opa1con opaon ? ? ? ? ? ? ? 0--- ---- 0--- ---- 11dh opa2con opaon ? ? ? ? ? ? ? 0--- ---- 0--- ---- legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by portc.
? 2004 microchip technology inc. preliminary ds41249a-page 47 PIC16F785 5.0 timer0 module the timer0 module timer/counter has the following features: 8-bit timer/counter readable and writable 8-bit software programmable prescaler internal or external clock select interrupt on overflow from ffh to 00h edge select for external clock figure 5-1 is a block diagram of the timer0 module and the prescaler shared with the wdt. 5.1 timer0 operation timer mode is selected by clearing the t0cs bit (option_reg<5>). in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if tmr0 is written, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting the t0cs bit (option_reg<5>). in this mode, the timer0 module will increment either on every rising or falling edge of pin ra2/an2/t0cki/int/c1out. the incrementing edge is determined by the source edge (t0se) control bit (option_reg<4>). clearing the t0se bit selects the rising edge. 5.2 timer0 interrupt a timer0 interrupt is generated when the tmr0 register timer/counter overflows from ffh to 00h. this overflow sets the t0if bit (intcon<2>). the interrupt can be masked by clearing the t0ie bit (intcon<5>). the t0if bit must be cleared in software by the timer0 module interrupt service routine before re-enabling this interrupt. the timer0 interrupt cannot wake the processor from sleep since the timer is shut-off during sleep. figure 5-1: block diagram of the timer0/wdt prescaler note: additional information on the timer0 module is available in the picmicro ? mid-range reference manual , (ds33023). note 1: counter mode has specific external clock requirements. additional information on these requirements is available in the picmicro ? mid-range reference manual , (ds33023). 2: the ansel0 (91h) register must be initialized to configure an analog channel as a digital input. pins configured as analog inputs will read ? 0 ?. t0se (1) clkout tmr0 watchdog timer wdt time-out ps<0:2> (1) wdte data bus set flag bit t0if on overflow t0cs (1) note 1: t0se, t0cs, psa, ps<2:0> are bits in the option_reg (see register 2-2 on page 16). 2: wdtps<3:0> are bits in the wdtcon register (see register 15-2 on page 118). 0 1 0 1 0 1 sync 2 cycles 8 8 8-bit prescaler 0 1 (= f osc /4) psa (1) psa (1) psa (1) 16-bit prescaler 16 wdtps<3:0> (2) 31 khz intrc swdten ra2/an2/t0cki/int/c1out
PIC16F785 ds41249a-page 48 preliminary ? 2004 microchip technology inc. 5.3 using timer0 with an external clock when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki, with the internal phase clocks, is accom- plished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks. therefore, it is necessary for t0cki to be high for at least 2t osc (and a small rc delay of 20 ns) and low for at least 2t osc (and a small rc delay of 20 ns). refer to the electrical specification of the desired device. 5.4 prescaler an 8-bit counter is available as a prescaler for the timer0 module, or as a postscaler for the watchdog timer. for simplicity, this counter will be referred to as ?prescaler? throughout this data sheet. the prescaler assignment is controlled in software by the control bit psa (option_reg<3>). clearing the psa bit will assign the prescaler to timer0. prescale values are selectable via the ps<2:0> bits (option_reg<2:0>). the prescaler is not readable or writable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf 1, movwf 1, bsf 1,x....etc. ) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the watchdog timer. 5.4.1 switching prescaler assignment the prescaler assignment is fully under software control (i.e., it can be changed ?on the fly? during program execution). to avoid an unintended device reset, the following instruction sequence (example 5-2 and example 5-3) must be executed when changing the prescaler assignment between timer0 and wdt. example 5-2: changing prescaler (timer0 wdt) to change prescaler from the wdt to the tmr0 module, use the sequence shown in example 5-3. this precaution must be taken even if the wdt is disabled. example 5-3: changing prescaler (wdt timer0) table 5-1: registers associated with timer0 bcf status,rp0 ;bank 0 bcf status,rp1 ; clrwdt ;clear wdt clrf tmr0 ;clear tmr0 and ; prescaler bsf status,rp0 ;bank 1 movlw b?00101111? ;required if desired movwf option_reg ; ps2:ps0 is clrwdt ; 000 or 001 ; movlw b?00101xxx? ;set postscaler to movwf option_reg ; desired wdt rate bcf status,rp0 ;bank 0 clrwdt ;clear wdt and ; prescaler bsf status,rp0 ;bank 1 bcf status,rp1 ; movlw b?xxxx0xxx? ;select tmr0, ; prescale, and ; clock source movwf option_reg ; bcf status,rp0 ;bank 0 addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 01h, 101h tmr0 timer0 module register xxxx xxxx uuuu uuuu 0bh, 8bh intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 81h, 181h option_reg rapu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 91h ansel0 ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 1111 1111 1111 1111 85h, 185h trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 legend: ? = unimplemented locations, read as ?0?, u = unchanged, x = unknown. shaded cells are not used by the timer0 module.
? 2004 microchip technology inc. preliminary ds41249a-page 49 PIC16F785 6.0 timer1 module with gate control the timer1 module is the 16 bit counter of the PIC16F785. figure 6-1 shows the basic block diagram of the timer1 module. timer1 has the following features: 16-bit timer/counter (tmr1h:tmr1l) readable and writable internal or external clock selection synchronous or asynchronous operation interrupt on overflow from ffffh to 0000h wake-up upon overflow (asynchronous mode) optional external enable input - selectable gate source; t1g or c2 output (t1gss) - selectable gate polarity (t1ginv) optional lp oscillator the timer1 control register (t1con), shown in register 6-1, is used to enable/disable timer1 and select the various features of the timer1 module. figure 6-1: timer1 on the pi c16f785 block diagram note: additional information on timer modules is available in the picmicro ? mid-range reference manual , (ds33023). tmr1h tmr1l oscillator t1sync tmr1cs t1ckps<1:0> sleep input f osc /4 internal clock prescaler 1, 2, 4, 8 synchronize det 1 0 0 1 synchronized clock input 2 set flag bit tmr1if on overflow tmr1 (1) tmr1on tmr1ge tmr1on tmr1ge intosc t1oscen without clkout * 1 0 syncc2out (2) t1gss t1ginv to c2 comparator module tmr1 clock * st buffer is low power type when using lp osc, or high-speed type when using t1cki. note 1: timer 1 increments on the rising edge. 2: syncc2out is the synchronized output from comparator 2 (see figure 9-2 on page 64). ra5/t1cki/osc1/clkin ra4/an3/t1g/osc2/clkout
PIC16F785 ds41249a-page 50 preliminary ? 2004 microchip technology inc. 6.1 timer1 modes of operation timer1 can operate in one of three modes: 16-bit timer with prescaler 16-bit synchronous counter 16-bit asynchronous counter in timer mode, timer1 is incremented on every instruc- tion cycle. in counter mode, timer1 is incremented on the rising edge of the external clock input t1cki. in addition, the counter mode clock can be synchronized to the microcontroller system clock or run asynchronously. in counter and timer modules, the counter/timer clock can be gated by the timer 1 gate, which can be selected as either the t1g pin or comparator 2 output. if an external clock oscillator is needed (and the microcontroller is using the lp oscillator or intosc without clkout), timer1 can use the lp oscillator as a clock source. 6.2 timer1 interrupt the timer1 register pair (tmr1h:tmr1l) increments to ffffh and rolls over to 0000h. when timer1 rolls over, the timer1 interrupt flag bit (pir1<0>) is set. to enable the interrupt on rollover, you must set these bits: timer1 interrupt enable bit (pie1<0>) peie bit (intcon<6>) gie bit (intcon<7>) the interrupt is cleared by clearing the tmr1if in the interrupt service routine. 6.3 timer1 prescaler timer1 has four prescaler options allowing 1, 2, 4, or 8 divisions of the clock input. the t1ckps bits (t1con<5:4>) control the prescale counter. the prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to tmr1h or tmr1l. 6.4 timer1 gate timer1 gate source is software configurable to be t1g pin or the output of comparator 2. this allows the device to directly time external events using t1g or analog events using comparator 2. see cm2con1 (register 9-3) for selecting the timer1 gate source. this feature can simplify the software for a delta-sigma a/d converter and many other applications. for more information on delta-sigma a/d converters, see the microchip web site (www.microchip.com). timer1 gate can be inverted using the t1ginv bit (t1con<7>), whether it originates from the t1g pin or comparator 2 output. this configures timer1 to measure either the active high or active low time between events. figure 6-2: timer1 incrementing edge note: in counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge. note: the tmr1h:tmr1l register pair and the tmr1if bit should be cleared before enabling interrupts. note: tmr1ge bit (t1con<6>) must be set to use either t1g or c2out as the timer1 gate source. see register 9-3 for more information on selecting the timer1 gate source. t1cki = 1 when tmr1 enabled t1cki = 0 when tmr1 enabled note 1: arrows indicate counter increments. 2: in counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
? 2004 microchip technology inc. preliminary ds41249a-page 51 PIC16F785 register 6-1: t1con ? timer1 control regi ster (address: 10h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 t1ginv tmr1ge t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 bit 7 t1ginv: timer1 gate invert bit (1) 1 = timer1 gate is high true (see bit 6) 0 = timer1 gate is low true (see bit 6) bit 6 tmr1ge: timer1 gate enable bit (2) if tmr1on = 0 : this bit is ignored if tmr1on = 1 : 1 = timer1 is on if timer1 gate is true (see bit 7) 0 = timer1 is on independent of timer1 gate bit 5-4 t1ckps<1:0>: timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: lp oscillator enable control bit if system clock is intosc without clkout or lp mode: 1 = lp oscillator is enabled for timer1 clock 0 = lp oscillator is off else: this bit is ignored bit 2 t1sync : timer1 external clock input synchronization control bit tmr1cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input tmr1cs = 0 : this bit is ignored. timer1 uses the internal clock. bit 1 tmr1cs: timer1 clock source select bit 1 = external clock from t1cki pin (on the rising edge) 0 = internal clock (f osc /4) bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 = stops timer1 note 1: t1ginv bit inverts the timer1 gate logic, regardless of source. 2: tmr1ge bit must be set to use either t1g pin or c2out, as selected by t1gss bit (cm2con1<1>), as a timer1 gate source. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC16F785 ds41249a-page 52 preliminary ? 2004 microchip technology inc. 6.5 timer1 operation in asynchronous counter mode if control bit t1sync (t1con<2>) is set, the external clock input is not synchronized. the timer continues to increment asynchronous to the internal phase clocks. the timer will continue to run during sleep and can generate an interrupt on overflow, which will wake-up the processor. however, special precautions in software are needed to read/write the timer ( section 6.5.1 ?reading and writing timer1 in asynchronous counter mode? ). 6.5.1 reading and writing timer1 in asynchronous counter mode reading tmr1h or tmr1l while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write conten- tion may occur by writing to the timer registers, while the register is incrementing. this may produce an unpredictable value in the timer register. reading the 16-bit value requires some care. examples in the picmicro ? mid-range mcu family reference manual (ds33023) show how to read and write timer1 when it is running in asynchronous mode. 6.6 timer1 oscillator a crystal oscillator circuit is built-in between pins osc1 (input) and osc2 (amplifier output). it is enabled by setting control bit t1oscen (t1con<3>). the oscillator is a low power oscillator rated for 32.768 khz. it will continue to run during sleep. it is primarily intended for a 32.768 khz tuning fork crystal. the timer1 oscillator is shared with the system lp oscillator. thus, timer1 can use this mode only when the primary system clock is also the lp oscillator or is derived from the internal oscillator. as with the system lp oscillator, the user must provide a software time delay to ensure proper oscillator start-up. sleep mode will not disable the system clock when the system clock and timer1 share the lp oscillator. trisa<5> and trisa<4> bits are set when the timer1 oscillator is enabled. ra5 and ra4 read as ? 0 ? and trisa<5> and trisa<4> bits read as ? 1 ?. 6.7 timer1 operation during sleep timer1 can only operate during sleep when setup in asynchronous counter mode. in this mode, an external crystal or clock source can be used to increment the counter. to setup the timer to wake the device: timer1 must be on (t1con<0>) tmr1ie bit (pie1<0>) must be set peie bit (intcon<6>) must be set the device will wake-up on an overflow. if the gie bit (intcon<7>) is set, the device will wake-up and jump to the interrupt service routine (0004h) on an overflow. if the gie bit is clear, execution will continue with the next instruction. table 6-1: registers associated with timer1 note: the ansel0 (91h) register must be initial- ized to configure an analog channel as a digital input. pins configured as analog inputs will read ? 0 ?. note: the oscillator requires a start-up and stabilization time before use. thus, t1oscen should be set and a suitable delay observed prior to enabling timer 1. addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 0ch pir1 eeif adif ccp1if c2if c1if osfif tmr2if tmr1if 0000 0000 0000 0000 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ginv tmr1ge t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 uuuu uuuu 1ah cm2con1 mc1out mc2out ? ? ? ?t1gss c2sync 00-- --10 00-- --10 8ch pie1 eeie adie ccp1ie c2ie c1ie osfie tmr2ie tmr1ie 0000 0000 0000 0000 91h ansel0 ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, ? = unimplemented, read as ' 0 '. shaded cells are not used by the timer1 module.
? 2004 microchip technology inc. preliminary ds41249a-page 53 PIC16F785 7.0 timer2 module the timer2 module timer is an 8-bit timer with the following features: 8-bit timer (tmr2 register) 8-bit period register (pr2) readable and writable (both registers) software programmable prescaler (1:1, 1:4, 1:16) software programmable postscaler (1:1 to 1:16 by 1?s) interrupt on tmr2 match with pr2 timer2 has a control register shown in register 7-1. tmr2 can be shut-off by clearing control bit tmr2on (t2con<2>) to minimize power consumption. figure 7-1 is a simplified block diagram of the timer2 module. the prescaler and postscaler selection of timer2 are controlled by this register. 7.1 timer2 operation timer2 can be used as the pwm time base for the pwm mode of the ccp module. the tmr2 register is readable and writable, and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits t2ckps<1:0> (t2con<1:0>). the match output of tmr2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr2 interrupt (latched in flag bit tmr2if, (pir1<1>)). the prescaler and postscaler counters are cleared when any of the following occurs: a write to the tmr2 register a write to the t2con register any device reset (power-on reset, mclr reset, watchdog timer reset or brown-out reset) tmr2 is not cleared when t2con is written. register 7-1: t2con ? timer2 control register (address: 12 h ) u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 bit 7 unimplemented: read as ? 0 ? bit 6-3 toutps<3:0>: timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale 1111 = 1:16 postscale bit 2 tmr2on: timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps<1:0>: timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC16F785 ds41249a-page 54 preliminary ? 2004 microchip technology inc. 7.2 timer2 interrupt the timer2 module has an 8-bit period register, pr2. timer2 increments from 00h until it matches pr2 and then resets to 00h on the next increment cycle. pr2 is a readable and writable register. the pr2 register is initialized to ffh upon reset. figure 7-1: timer2 block diagram table 7-1: registers associated with timer2 addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 0ch pir1 eeif adif ccp1if c2if c1if osfif tmr2if tmr1if 0000 0000 0000 0000 11h tmr2 holding register for the 8-bit tmr2 register 0000 0000 0000 0000 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 8ch pie1 eeie adie ccp1ie c2ie c1ie osfie tmr2ie tmr1ie 0000 0000 0000 0000 92h pr2 timer2 module period register 1111 1111 1111 1111 legend: x = unknown, u = unchanged, ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer2 module. comparator tmr2 sets flag tmr2 output reset postscaler prescaler pr2 2 f osc /4 1:1 to 1:16 1:1, 1:4, 1:16 eq 4 bit tmr2if toutps<3:0> t2ckps<1:0>
? 2004 microchip technology inc. preliminary ds41249a-page 55 PIC16F785 8.0 capture/compare/pwm (ccp) module the capture/compare/pwm (ccp) module contains a 16-bit register which can operate as a: 16-bit capture register 16-bit compare register pwm master/slave duty cycle register capture/compare/pwm register1 (ccpr1) is comprised of two 8-bit registers: ccpr1l (low byte) and ccpr1h (high byte). the ccp1con register controls the operation of ccp. the special event trigger is generated by a compare match and will clear both tmr1h and tmr1l registers. table 8-1: ccp mode - timer resources required register 8-1: ccp1con ? ccp operation register (address: 15h) ccp mode timer resource capture compare pwm timer1 timer1 timer2 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 bit 7 bit 0 bit 7-6 unimplemented: read as ? 0 ?. bit 5-4 dc1b<1:0>: pwm duty cycle least significant bits capture mode: unused compare mode: unused pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccpr1l. bit 3-0 ccp1m<3:0>: ccp mode select bits 0000 = capture/compare/pwm off (resets ccp module) 0001 = unused (reserved) 0010 = compare mode, toggle output on match (ccp1if bit is set) 0011 = unused (reserved) 0100 = capture mode, every falling edge 0101 = capture mode, every rising edge 0110 = capture mode, every 4th rising edge 0111 = capture mode, every 16th rising edge 1000 = compare mode, set output on match (ccp1if bit is set) 1001 = compare mode, clear output on match (ccp1if bit is set) 1010 = compare mode, generate software interrupt on match (ccp1if bit is set, ccp1 pin is unaffected) 1011 = compare mode, trigger special event (ccp1if bit is set; tmr1 is reset, and a/d conversion is started if the a/d module is enabled. ccp1 pin is unaffected.) 110x = pwm mode: ccp1 output is high true. 111x = pwm mode: ccp1 output is low true. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC16F785 ds41249a-page 56 preliminary ? 2004 microchip technology inc. 8.1 capture mode in capture mode, ccpr1h:ccpr1l captures the 16-bit value of the tmr1 register when an event occurs on pin rc5/ccp1. an event is defined as one of the following and is configured by ccp1con<3:0>: every falling edge every rising edge every 4th rising edge every 16th rising edge when a capture is made, the interrupt request flag bit ccp1if (pir1<5>) is set. the interrupt flag must be cleared in software. if another capture occurs before the value in register ccpr1 is read, the old captured value is overwritten by the new captured value. 8.1.1 ccp1 pin configuration in capture mode, the rc5/ccp1 pin should be config- ured as an input by setting the trisc<5> bit. figure 8-1: capture mode operation block diagram 8.1.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode for the ccp module to use the capture feature. in asynchronous counter mode, the capture operation may not work. 8.1.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep bit ccp1ie (pie1<5>) clear to avoid false interrupts and should clear the flag bit ccp1if (pir1<5>) following any such change in operating mode. 8.1.4 ccp prescaler there are four prescaler settings specified by bits ccp1m<3:0> (ccp1con<3:0>). whenever the ccp module is turned off, or the ccp module is not in cap- ture mode, the prescaler counter is cleared. any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. example 8-1 shows the recom- mended method for switching between capture prescalers. this example also clears the prescaler counter and will not generate the ?false? interrupt. example 8-1: changing between capture prescalers note: if the rc5/ccp1 pin is configured as an output, a write to the port can cause a capture condition. ccpr1h ccpr1l tmr1h tmr1l set flag bit ccp1if (pir1<5>) capture enable q?s ccp1con<3:0> prescaler 1, 4, 16 and edge detect pin rc5/ccp1 clrf ccp1con ;turn ccp module off movlw new_capt_ps ;load the w reg with ; the new prescaler ; move value and ccp on movwf ccp1con ;load ccp1con with this ; value
? 2004 microchip technology inc. preliminary ds41249a-page 57 PIC16F785 8.2 compare mode in compare mode, the 16-bit ccpr1 register value is constantly compared against the tmr1 register pair value. when a match occurs, the rc5/ccp1 pin is: driven high driven low remains unchanged the action on the pin is based on the value of control bits ccp1m<3:0> (ccp1con<3:0>). at the same time, interrupt flag bit ccp1if (pir1<5>) is set. figure 8-2: compare mode operation block diagram 8.2.1 ccp1 pin configuration the user must configure the rc5/ccp1 pin as an output by clearing the trisc<5> bit. 8.2.2 timer1 mode selection timer1 must be running in timer mode or synchro- nized counter mode if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 8.2.3 software interrupt mode when generate software interrupt mode is chosen (ccp1m<3:0> = 1010 ), the rc5/ccp1 pin is not affected. the ccp1if (pir1<5>) bit is set, causing a ccp interrupt (if enabled). see register 8-1. 8.2.4 special event trigger in this mode (ccp1m<3:0> = 1011 ), an internal hardware trigger is generated, which may be used to initiate an action. see register 8-1. the special event trigger output of ccp resets the tmr1 register pair. this allows the ccpr1 register to effectively be a 16-bit programmable period register for timer1. the special event trigger output also starts an a/d conversion (if the a/d module is enabled). table 8-2: registers associated with capture, compare, and timer1 ccpr1h ccpr1l tmr1h tmr1l comparator qs r output logic special event trigger set flag bit ccp1if (pir1<5>) match trisc<5> ccp1con<3:0> mode select output enable pin special event trigger will: clear tmr1h and tmr1l registers not set interrupt flag bit tmr1f (pir1<0>) set the go/done bit (adcon0<1>) rc5/ccp1 4 note: clearing the ccp1con register will force the rc5/ccp1 compare output latch to the default low level. this is not the portc i/o data latch. note: the special event trigger from the ccp module will not set interrupt flag bit tmr1if (pir1<0>). addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh 8bh intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 0ch pir1 eeif adif ccp1if c2if c1if osfif tmr2if tmr1if 0000 0000 0000 0000 0eh tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 0fh tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 10h t1con t1ginv tmr1ge t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 uuuu uuuu 1ah cm2con1 mc1out mc2out ? ? ? ?t1gss c2sync 00-- --10 00-- --10 13h ccpr1l capture/compare/pwm register1 low byte xxxx xxxx uuuu uuuu 14h ccpr1h capture/compare/pwm register1 high byte xxxx xxxx uuuu uuuu 15h ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 --00 0000 --00 0000 87h, 187h trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 --11 1111 --11 1111 8ch pie1 eeie adie ccp1ie c2ie c1ie osfie tmr2ie tmr1ie 0000 0000 0000 0000 legend: ? = unimplemented locations, read as ? 0 ?, u = unchanged, x = unknown. shaded cells are not used by the capture, compare or timer1 module.
PIC16F785 ds41249a-page 58 preliminary ? 2004 microchip technology inc. 8.3 ccp pwm mode in pulse width modulation (pwm) mode, the ccp module produces up to a 10-bit resolution pwm output on the rc5/ccp1 pin. since the rc5/ccp1 pin is multiplexed with the portc data latch, the trisc<5> must be cleared to make the rc5/ccp1 pin an output. figure 8-3 shows a simplified block diagram of pwm operation. for a step by step procedure on how to set up the ccp module for pwm operation, see section 8.3.5 ?setup for pwm operation? . figure 8-3: simplified pwm block diagram the pwm output (figure 8-4) has a time base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 8-4: ccp pwm output 8.3.1 pwm period the pwm period is specified by writing to the pr2 register. the pwm period can be calculated using the formula of equation 8-1. equation 8-1: pwm frequency is defined as 1 / [pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: tmr2 is cleared the rc5/ccp1 pin is set. (exception: if pwm duty cycle = 0%, the pin will not be set) the pwm duty cycle is latched from ccpr1l into ccpr1h 8.3.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr1l register and to the dc1b<1:0> (ccp1con<5:4>) bits. up to 10 bits of resolution is available. the ccpr1l contains the eight msbs and the dc1b<1:0> contains the two lsbs. ccpr1l and dc1b<1:0> can be written to at any time. in pwm mode, ccpr1h is a read-only register. this 10-bit value is represented by ccpr1l (ccp1con<5:4>). equation 8-2 is used to calculate the pwm duty cycle in time. equation 8-2: note: clearing the ccp1con register will force the pwm output latch to the default inactive levels. this is not the portc i/o data latch. ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (1) rq s duty cycle registers ccp1con<5:4> clear timer2, toggle pwm pin and latch duty cycle note 1: the 8-bit timer tmr2 register is concate- nated with the 2-bit internal q clock, or 2 bits of the prescaler, to create the 10-bit time base. trisc<5> rc5/ccp1 period duty cycle tmr2 = 0 tmr2 = duty cycle tmr2 = pr2 note: the timer2 postscaler (see section 7.1 ?timer2 operation? ) is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different frequency than the pwm output. pwm period pr2 () 1 + [] 4t osc ? ? ? = (tmr2 prescale value) pwm duty cycle ccpr1l:ccp1con<5:4> () ? = t osc ? (tmr2 prescale value)
? 2004 microchip technology inc. preliminary ds41249a-page 59 PIC16F785 ccpr1l and dc1b<1:0> can be written to at any time, but the duty cycle value is not latched into ccpr1h until after a match between pr2 and tmr2 occurs (i.e. the period is complete). in pwm mode, ccpr1h is a read only register. the ccpr1h register and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. because of the buffering, the module waits until the timer resets, instead of starting immediately. this means that enhanced pwm waveforms do not exactly match the standard pwm waveforms, but are instead offset by one full instruction cycle (4 t osc ). when the ccpr1h and 2-bit latch match tmr2, concatenated with an internal 2-bit q clock or 2 bits of the tmr2 prescaler, the rc5/ccp1 pin is cleared. the maximum pwm resolution is a function of pr2 as shown by equation 8-3. equation 8-3: table 8-3: example pwm frequencies and resolutions (f osc = 20 mhz) 8.3.3 operation in sleep mode in sleep mode, all clock sources are disabled. timer2 will not increment, and the state of the module will not change. if the rc5/ccp1 pin is driving a value, it will continue to drive that value. when the device wakes up, it will continue from this state. 8.3.3.1 operation with fail-safe clock monitor if the fail-safe clock monitor is enabled, a clock failure will force the ccp to be clocked from the internal oscillator clock source, which may have a different clock frequency than the primary clock. see section 3.0 ?clock sources? for additional details. 8.3.4 effects of a reset any reset will force all ports to input mode and the ccp registers to their reset states. 8.3.5 setup for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. configure the pwm pin (rc5/ccp1) as an input by setting the trisc<5> bit. 2. set the pwm period by loading the pr2 register. 3. configure the ccp module for the pwm mode by loading the ccp1con register with the appropriate values. 4. set the pwm duty cycle by loading the ccpr1l register and ccp1con<5:4> bits. 5. configure and start tmr2: clear the tmr2 interrupt flag bit by clearing the tmr2if bit (pir1<1>). set the tmr2 prescale value by loading the t2ckps bits (t2con<1:0>). enable timer2 by setting the tmr2on bit (t2con<2>). 6. enable pwm output after a new pwm cycle has started: wait until tmr2 overflows (tmr2if bit is set). enable the rc5/ccp1 pin output by clearing the trisc<5> bit. note: if the pwm duty cycle value is longer than the pwm period, the assigned pwm pin(s) will remain unchanged. resolution 4 pr 21 + () [] log 2 () log ----------------------------------------- bits = pwm frequency 1.22 khz (1) 4.88 khz (1) 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescale (1, 4, 16) 16 4 1 1 1 1 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 6.6 note 1: changing duty cycle will cause a glitch.
PIC16F785 ds41249a-page 60 preliminary ? 2004 microchip technology inc. table 8-4: registers associated with ccp and timer2 addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 0bh, 8bh intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 0ch pir1 eeif adif ccp1if c2if c1if osfif tmr2if tmr1if 0000 0000 0000 0000 11h tmr2 timer2 module register 0000 0000 0000 0000 12h t2con ? toutps3 toutps2 toutps1 toutps0 tmr2on t2ckps1 t2ckps0 -000 0000 -000 0000 13h ccpr1l capture/compare/pwm register1 low byte xxxx xxxx uuuu uuuu 14h ccpr1h capture/compare/pwm register1 high byte xxxx xxxx uuuu uuuu 15h ccp1con ? ? dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 0000 0000 87h trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 --11 1111 --11 1111 8ch pie1 eeie adie ccp1ie c2ie c1ie osfie tmr2ie tmr1ie 0000 0000 0000 0000 92h pr2 timer2 module period register 1111 1111 1111 1111 legend: ? = unimplemented locations, read as ? 0 ?, u = unchanged, x = unknown. shaded cells are not used by the ccp or timer2 modules.
? 2004 microchip technology inc. preliminary ds41249a-page 61 PIC16F785 9.0 comparator module the comparator module has two separate voltage comparators: comparator c1 and comparator c2. each comparator offers the following list of features: control and configuration register comparator output available externally programmable output polarity interrupt-on-change flags wake-up from sleep configurable as feedback input to the pwm programmable four input multiplexer programmable two input reference selections programmable speed/power output synchronization to timer1 clock input (comparator c2 only) 9.1 control registers both comparators have separate control and configura- tion registers: cm1con0 for c1 and cm2con0 for c2. in addition, comparator c2 has a second control register, cm2con1, for synchronization control and simultaneous reading of both comparator outputs. 9.1.1 comparator c1 control register the cm1con0 register (shown in register 9-1) contains the control and status bits for the following: comparator enable comparator input selection comparator reference selection output mode comparator speed setting c1on (cm1con0<7>) enables comparator c1 for operation. bits c1ch<1:0> (cm1con0<1:0>) select the compar- ator input from the four analog pins an<7:5,1>. setting c1r (cm1con0<2>) selects the c1v ref out- put of the comparator voltage reference module as the reference voltage for the comparator. clearing c1r selects the c1in+ input on the ra0/an0/c1in+/icspdat pin. the output of the comparator is available internally via the c1out flag (cm1con0<6>). to make the output available for an external connection, the c1oe bit (cm1con0<5>) must be set. the polarity of the comparator output can be inverted by setting the c1pol bit (cm1con0<4>). clearing c1pol results in a non-inverted output. a complete table showing the output state versus input conditions and the polarity bit is shown in table 9-1. c1sp (cm1con0<3>) configures the speed of the comparator. when c1sp is set, the comparator oper- ates at its normal speed. clearing c1sp operates the comparator in a slower, low-power mode. note: to use an<7:5,1> as analog inputs the appropriate bits must be programmed to ? 1 ? in the ansel0 register. table 9-1: c1output state versus input conditions input condition c1pol c1out c1vn > c1vp 0 0 c1vn < c1vp 0 1 c1vn > c1vp 1 1 c1vn < c1vp 1 0 note 1: the internal output of the comparator is latched at the end of each instruction cycle. external outputs are not latched. 2: the c1 interrupt will operate correctly with c1oe set or cleared. 3: to output c1 on ra2/an2/t0cki/int/c1out: (c1oe=1) & (c1on=1) & (trisa<2>=0).
PIC16F785 ds41249a-page 62 preliminary ? 2004 microchip technology inc. figure 9-1: comparator c1 simplified block diagram note 1: when c1on = 0 , the c1 comparator will produce a ? 0 ? output to the xor gate. mux c1 c1pol c1out to pwm logic 0 1 2 3 c1on (1) c1sp c1ch<1:0> 2 0 1 c1r c1oe c1v ref mux rd_cm1con0 set c1if to c1vn c1vp ra2/an2/t0cki/int/c1out ra1/an1/c12in0-/v ref /icspclk rc1/an5/c12in1-/ph1 rc2/an6/c12in2-/op2 rc3/an7/c12in3-/op1 ra0/an0/c1in+/icspdat dq en q1 data bus c1pol dq en cl q3*rd_cm1con0 nreset
? 2004 microchip technology inc. preliminary ds41249a-page 63 PIC16F785 register 9-1: comparator c1 control register 0 (cm1con0: 119h) r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 c1on c1out c1oe c1pol c1sp c1r c1ch1 c1ch0 bit 7 bit 0 bit 7 c1on: comparator c1 enable bit 1 = c1 comparator is enabled 0 = c1 comparator is disabled bit 6 c1out: comparator c1 output bit if c1pol = 1 (inverted polarity): c1out = 1 , c1vp < c1vn c1out = 0 , c1vp > c1vn if c1pol = 0 (non-inverted polarity): c1out = 1 , c1vp > c1vn c1out = 0 , c1vp < c1vn bit 5 c1oe: comparator c1 output enable bit 1 = c1out is present on the ra2/an2/t0cki/int/c1out pin (1) 0 = c1out is internal only bit 4 c1pol: comparator c1 output polarity select bit 1 = c1out logic is inverted 0 = c1out logic is not inverted bit 3 c1sp: comparator c1 speed select bit 1 = c1 operates in normal speed mode 0 = c1 operates in low-power, slow speed mode bit 2 c1r: comparator c1 reference select bit (non-inverting input) 1 = c1vp connects to c1v ref output 0 = c1vp connects to ra0/an0/c1in+/icspdat bit 1-0 c1ch<1:0>: comparator c1 channel select bit 00 = c1vn of c1 connects to ra1/an1/c12in0-/v ref /icspclk 01 = c1vn of c1 connects to rc1/an5/c12in1-/ph1 10 = c1vn of c1 connects to rc2/an6/c12in2-/op2 11 = c1vn of c1 connects to rc3/an7/c12in3-/op1 note 1: c1out will only drive ra2/an2/t0cki/int/c1out if: (c2oe = 1) & (c2on = 1) & (trisa<2> = 0) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC16F785 ds41249a-page 64 preliminary ? 2004 microchip technology inc. 9.1.2 comparator c2 control registers the cm2con0 register is a functional copy of the cm1con0 register described in section 9.1.1. a sec- ond control register, cm2con1, is also present for control of an additional synchronizing feature, as well as mirrors of both comparator outputs. 9.1.2.1 control register cm2con0 the cm2con0 register, shown in register 9-2, con- tains the control and status bits for comparator c2. setting c2on (cm2con0<7>) enables comparator c2 for operation. bits c2ch<1:0> (cm2con0<1:0>) select the compar- ator input from the four analog pins, an<7:5,1>. c2r (cm2con0<2>) selects the reference to be used with the comparator. setting c2r (cm2con0<2>) selects the c2v ref output of the comparator voltage reference module as the reference voltage for the com- parator. clearing c2r selects the c2in+ input on the rc0/an4/c2in+ pin. the output of the comparator is available internally via the c2out bit (cm2con0<6>). to make the output available for an external connection, the c2oe bit (cm2con0<5>) must be set. the comparator output, c2out, can be inverted by setting the c2pol bit (cm2con0<4>). clearing c2pol results in a non-inverted output. a complete table showing the output state versus input conditions and the polarity bit is shown in table 9-2. c2sp (cm2con0<3>) configures the speed of the comparator. when c2sp is set, the comparator oper- ates at its normal speed. clearing c2sp operates the comparator in low-power mode. figure 9-2: comparator c2 simplified block diagram note 1: to use an<7:5,1> as analog inputs, the appropriate bits must be programmed to 1 in the ansel0 register. table 9-2: c2 output state versus input conditions input condition c2pol c2out c2vn > c2vp 0 0 c2vn < c2vp 0 1 c2vn > c2vp 1 1 c2vn < c2vp 1 0 note 1: the internal output of the comparator is latched at the end of each instruction cycle. external outputs are not latched. 2: the c2 interrupt will operate correctly with c2oe set or cleared. an external output is not required for the c2 interrupt. 3: for c2 output on rc4/c2out/ph2: (c2oe=1) & (c2on=1) & (trisa<4>=0). mux c2 c2pol c2out to pwm logic 0 1 2 3 c2on (1) c2sp c2ch<1:0> 2 0 1 c2r from tmr1 clock note 1: when c2on = 0, the c2 comparator will produce a ? 0 ? output to the xor gate. 2: timer1 gate control (see figure 6-2 on page 50). c20e c2v ref mux dq en dq en cl dq rd_cm2con0 q3*rd_cm2con0 q1 set c2if to nreset c2vn c2vp rc4/c2out/ph2 rc0/an4/c2in+ ra1/an1/c12in0-/v ref /icspclk rc1/an5/c12in1-/ph1 rc2/an6/c12in2-/op2 rc3/an7/c12in3-/op1 0 1 c2sync syncc2out (2) c2pol data bus mux
? 2004 microchip technology inc. preliminary ds41249a-page 65 PIC16F785 register 9-2: comparator c2 control register 0 (cm2con0: 11ah) r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 c2on c2out c2oe c2pol c2sp c2r c2ch1 c2ch0 bit 7 bit 0 bit 7 c2on: comparator c2 enable bit 1 = c2 comparator is enabled 0 = c2 comparator is disabled bit 6 c2out: comparator c2 output bit if c2pol = 1 (inverted polarity): c2out = 1 , c2vp < c2vn c2out = 0 , c2vp > c2vn if c2pol = 0 (non-inverted polarity): c2out = 1 , c2vp > c2vn c2out = 0 , c2vp < c2vn bit 5 c2oe: comparator c2 output enable bit 1 = c2out is present on rc4/c2out/ph2 (1) 0 = c2out is internal only bit 4 c2pol: comparator c2 output polarity select bit 1 = c2out logic is inverted 0 = c2out logic is not inverted bit 3 c2sp: comparator c2 speed select bit 1 = c2 operates in normal speed mode 0 = c2 operates in low power, slow speed mode. bit 2 c2r: comparator c2 reference select bits (non-inverting input) 1 = c2vp connects to c2v ref 0 = c2vp connects to rc0/an4/c2in+ bit 1-0 c2ch<1:0>: comparator c2 channel select bits 00 = c2vn of c2 connects to ra1/an1/c12in0-/v ref /icspclk 01 = c2vn of c2 connects to rc1/an5/c12in1-/ph1 10 = c2vn of c2 connects to rc2/an6/c12in2-/op2 11 = c2vn of c2 connects to rc3/an7/c12in3-/op1 note 1: c2out will only drive rc4/c2out/ph2 if: (c2oe = 1) & (c2on = 1) & (trisc<4> = 0) legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC16F785 ds41249a-page 66 preliminary ? 2004 microchip technology inc. 9.1.2.2 control register cm2con1 comparator c2 has one additional feature: its output can be synchronized to the timer1 clock input. setting c2sync (cm2con1<0>) synchronizes the output of comparator 2 to the falling edge of timer 1?s clock input (see figure 9-2 and register 9-3). the cm2con1 register also contains mirror copies of both comparator outputs, mc1out and mc2out (cm2con1<7:6>). the ability to read both outputs simultaneously from a single register eliminates the timing skew of reading separate registers. register 9-3: comparator c2 control regist er 1 (cm2con1: 11bh) note 1: obtaining the status of c1out or c2out by reading cm1con1 does not affect the comparator interrupt mismatch registers. r-0 r-0 u-0 u-0 u-0 u-0 r/w-1 r/w-0 mc1out mc2out ? ? ? ? t1gss c2sync bit 7 bit 0 bit 7 mc1out: mirror copy of c1out (cm1con0<6>) bit 6 mc2out: mirror copy of c2out (cm2con0<6>) bit 5-2 unimplemented: read as ?0? bit 1 t1gss: timer1 gate source select bit 1 = timer1 gate source is ra4/an3/t1g/osc2/clkout 0 = timer1 gate source is syncc2out. bit 0 c2sync: c2 output synchronous mode bit 1 = c2 output is synchronous to falling edge of tmr1 clock 0 = c2 output is asynchronous legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds41249a-page 67 PIC16F785 9.2 comparator outputs the comparator outputs are read through the cm1con0, com2con0 or cm2con1 registers. cm1con0 and cm2con0 each contain the individ- ual comparator output of comparator 1 and compara- tor 2, respectively. cm2con2 contains a mirror copy of both comparator outputs facilitating a simultaneous read of both comparators. these bits are read-only. the comparator outputs may also be directly output to the ra2/an2/t0cki/int/c1out and rc4/c2out/ph2 i/o pins. when enabled, multiplex- ers in the output path of the ra2 and rc4 pins will switch and the output of each pin will be the unsyn- chronized output of the comparator. the uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifica- tions. figure 9-1 and figure 9-2 show the output block diagrams for comparators 1 and 2, respectively. the tris bits will still function as an output enable/disable for the ra2/an2/t0cki/int/c1out and rc4/c2out/ph2 pins while in this mode. the polarity of the comparator outputs can be changed using the c1pol and c2pol bits (cmxcon0<4>). timer1 gate source can be configured to use the t1g pin or comparator 2 output as selected by the t1gss bit (cm2con1<1>). the timer1 gate feature can be used to time the duration or interval of analog events. the output of comparator 2 can also be synchronized with timer1 by setting the c2sync bit (cm2con1<0>). when enabled, the output of com- parator 2 is latched on the falling edge of timer1 clock source. if a prescaler is used with timer1, comparator 2 is latched after the prescaler. to prevent a race con- dition, the comparator 2 output is latched on the falling edge of the timer1 clock source and timer1 incre- ments on the rising edge of its clock source. see the comparator 2 block diagram (figure 9-2) and the timer1 block diagram (figure 6-1) for more informa- tion. it is recommended to synchronize comparator 2 with timer1 by setting the c2sync bit when comparator 2 is used as the timer1 gate source. this ensures timer1 does not miss an increment if comparator 2 changes during an increment. 9.3 comparator interrupts the comparator interrupt flags are set whenever there is a change in the output value of its respective compar- ator. software will need to maintain information about the status of the output bits, as read from cm2con0<7:6>, to determine the actual change that has occurred. the cxif bits, pir1<4:3>, are the comparator interrupt flags. each comparator interrupt bit must be reset in software by clearing it to ? 0 ?. since it is also possible to write a ? 1 ? to this register, a simu- lated interrupt may be initiated. the cxie bits (pie1<4:3>) and the peie bit (intcon<6>) must be set to enable the interrupts. in addition, the gie bit must also be set. if any of these bits are cleared, the interrupt is not enabled, though the cxif bits will still be set if an interrupt condition occurs. the comparator interrupt of the PIC16F785 differs from previous designs in that the interrupt flag is set by the mismatch edge and not the mismatch level. this means that the interrupt flag can be reset without the additional step of reading or writing the cmxcon0 register to clear the mismatch registers. when the mismatch registers are not cleared, an interrupt will not occur when the comparator output returns to the previous state. when the mismatch registers are cleared, an interrupt will occur when the comparator returns to the previous state. 9.4 effects of reset a reset forces all registers to their reset state. this disables both comparators. note 1: if a change in the cmxcon0 register (cxout) should occur when a read operation is being executed (start of the q2 cycle), then the cxif (pir1<4:3>) interrupt flag may not get set. 2: when either comparator is first enabled, bias circuitry in the comparator module may cause an invalid output from the comparator until the bias circuitry is sta- ble. allow about 1 s for bias settling then clear the mismatch condition and inter- rupt flags before enabling comparator interrupts.
PIC16F785 ds41249a-page 68 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds41249a-page 69 PIC16F785 10.0 voltage references there are two voltage references available in the PIC16F785: the voltage referred to as the comparator reference (cv ref ) is a variable voltage based on v dd ; the voltage referred to as the vr reference (vr) is a fixed voltage derived from a stable bandgap source. each source may be individually routed internally to the comparators or output, buffered or unbuffered, on the ra1/an1/c12in0-/v ref /icspclk pin. 10.1 comparator reference the comparator module also allows the selection of an internally generated voltage reference for one of the comparator inputs. the vrcon register (register 10-1) controls the voltage reference module shown in figure 10-1. 10.1.1 configuring the voltage reference the voltage reference can output 32 distinct voltage levels, 16 in a high range and 16 in a low range. the following equation determines the output voltages: equation 10-1: 10.1.2 voltage reference accuracy/error the full range of v ss to v dd cannot be realized due to the construction of the module. the transistors on the top and bottom of the resistor ladder network (figure 10-1) keep cv ref from approaching v ss or v dd . the exception is when the module is disabled by clearing all cvroe, c1vren and c2vren bits. when disabled, the reference voltage is v ss when vr<3:0> is ? 0000 ? and the vrr (vrcon<5>) bit is set. this allows the comparators to detect a zero- crossing and not consume cv ref module current. the voltage reference is v dd derived and therefore, the cv ref output changes with fluctuations in v dd . the tested absolute accuracy of the comparator voltage ref- erence can be found in table 18-8. figure 10-1: comparator voltage reference block diagram vrr = 1 (low range): cv ref = vr<3:0> x v dd /24 vrr = 0 (high range): cv ref = (v dd /4) + (vr<3:0> x v dd /32) vrr 8r vr3:vr0 16-1 analog 8rrr rr c1v ref to 16 stages comparator 1 input cvren (1) v dd mux 0 1 c2v ref to comparator 2 input 0 1 vr 1.2 v c2vren c1vren cv ref cvroe note 1: see register 10-1, bits 3-0. 15 0
PIC16F785 ds41249a-page 70 preliminary ? 2004 microchip technology inc. register 10-1: voltage reference co ntrol register (vrcon: 99h) r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 c1vren c2vren vrr ? vr3 vr2 vr1 vr0 bit 7 bit 0 bit 7: c1vren : comparator 1 voltage reference enable bit (1) 1 = cv ref circuit powered on and routed to c1v ref input of comparator 1 0 = 1.2 volt vr routed to c1v ref input of comparator 1 bit 6: c2vren : comparator 2 voltage reference enable bit (1) 1 = cv ref circuit powered on and routed to c2v ref input of comparator 2 0 = 1.2 volt vr routed to c2v ref input of comparator 2 bit 5: vrr : comparator voltage reference cv ref range selection bit 1 = low range 0 = high range bit 4: unimplemented : read as ?0? bit 3-0: vr<3:0> : comparator voltage reference cv ref value selection 0 vr<3:0> 15 when vrr = 1 & cvren = 1: cv ref = (vr<3:0> x v dd / 24) when vrr = 0 & cvren = 1: cv ref = (v dd / 4) + (vr<3:0> x v dd / 32) when cxvren = 0: cxv ref = 1.2 volts from vr module note 1: when c1vren, c2vren and cvroe (register 10-2) are all low, the cv ref circuit is powered down and does not contribute to i dd current. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds41249a-page 71 PIC16F785 10.2 vr reference module the vr reference module generates a 1.2v nominal output voltage for use by the adc and comparators. the output voltage can also be brought out to the v ref pin for user applications. this module uses a bandgap as a reference. see table 18-9 for detailed specifica- tions. register 10-2 shows the control register for the vr module. register 10-2: voltage reference control register (refcon: 98h) u-0 u-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 ? ? bgst vrbb vren vroe cvroe ? bit7 bit0 bit 7-6: unimplemented: read as ? 0 ? bit 5: bgst: bandgap reference voltage stable flag bit 1 = reference is stable 0 = reference is not stable bit 4: vrbb: voltage reference buffer bypass bit 1 = v ref output is not buffered 0 = v ref output is buffered bit 3: vren: voltage reference enable bit (vr = 1.2v nominal) 1 = vr reference is enabled 0 = vr reference is disabled and does not consume any current bit 2: vroe: voltage reference output enable bit if cvroe = 0 : 1 = v ref output on ra1/an1/c12in0-/v ref /icspclk pin is 1.2 volt vr analog reference 0 = disabled, 1.2 volt vr analog reference is used internally only if cvroe = 1 : vroe has no effect. bit 1 cvroe : comparator voltage reference output enable bit (see figure 10-2) 1 = v ref output on ra1/an1/c12in0-/v ref /icspclk pin is cv ref voltage 0 = v ref output on ra1/an1/c12in0-/v ref /icspclk pin is controlled by vroe bit 0: unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? - bit as set ?0? = bit is cleared x = bit is unknown
PIC16F785 ds41249a-page 72 preliminary ? 2004 microchip technology inc. 10.2.1 vr stabilization period when the voltage reference module is enabled, it will require some time for the reference and its amplifier circuits to stabilize. the user program must include a small delay routine to allow the module to settle. see the electrical specifications section for the minimum delay requirement. the internal circuitry automatically recognizes when the voltage reference is required by the combination and purpose of various sfr control bits. the vren enable bit allows the user to keep the voltage refer- ence enabled even when sfr control bits would otherwise disable the reference. this precludes the need to wait for the voltage reference to stabilize when modules are switched in and out of service. figure 10-2: vr reference block diagram table 10-1: registers associated with the comparator and voltage reference modules ra1/an1/c12in0-/v ref vren voltage reference en rdy to c v ref mux bgst vr 1 0 1x analog buffer cv ref vrbb vr out cvroe (cvroe + (vren*vroe)) 1 0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 119h cm1con0 c1on c1out c1oe c1pol c1sp c1r c1ch1 c1ch0 0000 0000 0000 0000 11ah cm2con0 c2on c2out c2oe c2pol c2sp c2r c2ch1 c2ch0 0000 0000 0000 0000 11bh cm2con1 mc1out mc2out ? ? ? ? tigss c2sync 00-- --10 00-- --10 85h, 185h trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 87h, 187h trisc trisc7 trisc6 trisc5 trisc4 tris c3 trisc2 trisc1 trisc0 1111 1111 1111 1111 05h, 105h porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --xx xxxx --uu uuuu 07h, 107h portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu 91h ansel0 ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 1111 1111 1111 1111 0ch pir1 eeif adif ccp1if c2if c1if osfif tmr2if tmr1if 0000 ---0 0000 ---0 8ch pie1 eeie adie ccp1ie c2ie c1ie osfie tmr2ie tmr1ie 0000 ---0 0000 ---0 98h refcon ? ? bgst vrbb vren vroe cvroe ? --00 000- --00 000- 99h vrcon c1vren c2vren vrr ? vr3 vr2 vr1 vr0 000- 0000 000- 0000 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used for comparator.
? 2004 microchip technology inc. preliminary ds41249a-page 73 PIC16F785 11.0 operational amplifier (opa) module the opa module has the following features: two independent operational amplifiers external connections to all ports 3 mhz gain bandwidth product (gbwp) 11.1 control registers the opa1con register, shown in register 11-1, controls opa1. opa2con, shown in register 11-2, controls opa2. 11.2 opaxcon register the opa module is enabled by setting the opaon bit (opaxcon<7>). when enabled, opaon forces the output driver of rc3/an7/c12in3-/op1 for opa1, and rc2/an6/c12in2-/op2 for opa2, into tri-state to pre- vent contention between the driver and the opa output. figure 11-1: opa module block diagram note: when opa1 or opa2 is enabled, the rc3/an7/c12in3-/op1 pin, or rc2/an6/c12in2-/op2 pin respectively, is driven by the op amp output, not by the portc driver. refer to the electrical specifications for the op amp output drive capability. opa1 opa1con to adc and comparator muxs rc7/an9/op1+ rc6/an8/op1- rc3/an7/c12in3-/op1 opa2 opa2con to adc and comparator muxs rb5/an11/op2+ rb4/an10/op2- rc2/an6/c12in2-/op2
PIC16F785 ds41249a-page 74 preliminary ? 2004 microchip technology inc. register 11-1: op amp 1 control register (opa1con: 11ch) register 11-2: op amp 2 control register (opa2con: 11dh) r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 opaon ? ? ? ? ? ? ? bit 7 bit 0 bit 7 opaon: op amp enable bit 1 = op amp1 is enabled 0 = op amp1 is disabled bit 6-0 unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 opaon ? ? ? ? ? ? ? bit 7 bit 0 bit 7 opaon: op amp enable bit 1 = op amp2 is enabled 0 = op amp2 is disabled bit 6-0 unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds41249a-page 75 PIC16F785 11.3 effects of reset a device reset forces all registers to their reset state. this disables both op amps. 11.4 opa module performance common ac and dc performance specifications for the opa module: common mode voltage range leakage current input offset voltage open loop gain gain bandwidth product (gbwp) common mode voltage range is the specified voltage range for the opa+ and opa- inputs, for which the opa module will perform to within its specifications. the opa module is designed to operate with input voltages between 0 and v dd -1.4v. behavior for common mode voltages greater than v dd -1.4v, or below 0v, are beyond the normal operating range. leakage current is a measure of the small source or sink currents on the opa+ and opa- inputs. to mini- mize the effect of leakage currents, the effective imped- ances connected to the opa+ and opa- inputs should be kept as small as possible and equal. input offset voltage is a measure of the voltage differ- ence between the opa+ and opa- inputs in a closed loop circuit with the opa in its linear region. the offset voltage will appear as a dc offset in the output equal to the input offset voltage, multiplied by the gain of the circuit. the input offset voltage is also affected by the common mode voltage. open loop gain is the ratio of the output voltage to the differential input voltage, (opa+) - (opa-). the gain is greatest at dc and falls off with frequency. gain bandwidth product or gbwp is the frequency at which the open loop gain falls off to 0 db. table 11-1: registers associated with the opa module address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 11ch opa1con opaon ? ? ? ? ? ? ? 0--- ---- 0--- ---- 11dh opa2con opaon ? ? ? ? ? ? ? 0--- ---- 0--- ---- 91h ansel0 ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 1111 1111 1111 1111 93h ansel1 ? ? ? ? ans11 ans10 ans9 ans8 ---- 1111 ---- 1111 86h, 186h trisb trisb7 trisb6 trisb5 trisb4 ? ? ? ? 1111 ---- 1111 ---- 87h, 187h trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?. shaded cells are not used for the opa module.
PIC16F785 ds41249a-page 76 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds41249a-page 77 PIC16F785 12.0 analog-to-digital converter (a/d) module the analog-to-digital converter (a/d) allows conversion of an analog input signal to a 10-bit binary representa- tion of that signal. the PIC16F785 has twelve analog i/o inputs, plus two internal inputs, multiplexed into one sample and hold circuit. the output of the sample and hold is connected to the input of the converter. the con- verter generates a binary result via successive approx- imation and stores the result in a 10-bit register. the voltage reference used in the conversion is software selectable to either v dd or a voltage applied by the v ref pin. figure 12-1 shows the block diagram of the a/d on the PIC16F785. figure 12-1: a/d block diagram a/d v dd v ref adon (1) go/done vcfg = 1 vcfg = 0 chs<3:0> adresh adresl 10 10 adfm v ss ra0/an0/c1in+/icspdat ra1/an1/c12in0-/v ref /icspclk ra2/an2/t0cki/int/c1out ra4/an3/t1g/osc2/clkout rc0/an4/c2in+ rc1/an5/c12in1-/ph1 rc2/an6/c12in2-/op2 rc3/an7/c12in3-/op1 rc6/an8/op1- rc7/an9/op1+ rb4/an10/op2- rb5/an11/op2+ cv ref vr 0 13 note 1: when adon = ? 0 ? all input channels are disconnected from adc (no loading).
PIC16F785 ds41249a-page 78 preliminary ? 2004 microchip technology inc. 12.1 a/d configuration and operation there are four registers available to control the functionality of the a/d module: 1. ansel0 (register 12-1) 2. ansel1 (register 12-2) 3. adcon0 (register 12-3) 4. adcon1 (register 12-4) 12.1.1 analog port pins the ans<11:0> bits (ansel1<3:0> and ansel0<7:0>) and the trisa<4,2:0>, trisb<5:4> and trisc<7:6,3:0>> bits control the operation of the a/d port pins. set the corresponding trisx bits to ? 1 ? to set the pin output driver to its high-impedance state. likewise, set the corresponding ansx bit to disable the digital input buffer. 12.1.2 channel selection there are fourteen analog channels on the PIC16F785. the chs<3:0> bits (adcon0<5:2>) control which channel is connected to the sample and hold circuit. 12.1.3 voltage reference there are two options for the voltage reference to the a/d converter: either v dd is used or an analog voltage applied to v ref is used. the vcfg bit (adcon0<6>) controls the voltage reference selection. if vcfg is set, then the voltage on the v ref pin is the reference; otherwise, v dd is the reference. 12.1.4 conversion clock the a/d conversion cycle requires 11 t ad . the source of the conversion clock is software selectable via the adcs bits (adcon1<6:4>). there are seven possible clock options: f osc /2 f osc /4 f osc /8 f osc /16 f osc /32 f osc /64 f rc (dedicated internal oscillator) for correct conversion, the a/d conversion clock (1/t ad ) must be selected to ensure a minimum t ad of 1.6 s. table 12-1 shows a few t ad calculations for selected frequencies. table 12-1: t ad vs. device operating frequencies note: analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. a/d clock source (t ad ) device frequency operation adcs2:adcs0 20 mhz 5 mhz 4 mhz 1.25 mhz 2 t osc 000 100 ns (2) 400 ns (2) 500 ns (2) 1.6 s 4 t osc 100 200 ns (2) 800 ns (2) 1.0 s (2) 3.2 s 8 t osc 001 400 ns (2) 1.6 s 2.0 s 6.4 s 16 t osc 101 800 ns (2) 3.2 s 4.0 s 12.8 s (3) 32 t osc 010 1.6 s 6.4 s 8.0 s (3) 25.6 s (3) 64 t osc 110 3.2 s 12.8 s (3) 16.0 s (3) 51.2 s (3) a/d rc x11 2?6 s (1,4) 2?6 s (1,4) 2?6 s (1,4) 2?6 s (1,4) legend: shaded cells are outside of recommended range. note 1: the a/d rc source has a typical t ad time of 4 s for v dd > 3.0v. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: when the device frequency is greater than 1 mhz, the a/d rc clock source is only recommended if the conversion will be performed during sleep.
? 2004 microchip technology inc. preliminary ds41249a-page 79 PIC16F785 12.1.5 starting a conversion the a/d conversion is initiated by setting the go/done bit (adcon0<1>). when the conversion is complete, the a/d module: clears the go/done bit sets the adif flag (pir1<6>) generates an interrupt (if enabled) if the conversion must be aborted, the go/done bit can be cleared in software. the adresh:adresl registers will not be updated with the partially complete a/d conversion sample. instead, the adresh:adresl registers will retain the value of the previous conversion. after an aborted conversion, a 2t ad delay is required before another acquisition can be initiated. following the delay, an input acquisition is automatically started on the selected channel. figure 12-2: a/d conversion t ad cycles 12.1.6 conversion output the a/d conversion can be supplied in two formats: left or right justified. the adfm bit (adcon0<7>) controls the output format. figure 12-3 shows the output formats. figure 12-3: 10-bit a/d result format note: the go/done bit should not be set in the same instruction that turns on the a/d. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 9 set go bit holding capacitor is disconnected fr om analog input (typically 100 ns) b9 b8 b7 b6 b5 b4 b3 b2 t ad 10 t ad 11 b1 b0 t cy to t ad conversion starts adresh and adresl registers are loaded, go bit is cleared, adif bit is set, holding capacitor is connected to analog input adresh adresl (adfm = 0 )msb lsb bit 7bit 0bit 7bit 0 10-bit a/d result unimplemented: read as ? 0 ? (adfm = 1 ) msb lsb bit 7bit 0bit 7bit 0 unimplemented: read as ? 0 ? 10-bit a/d result
PIC16F785 ds41249a-page 80 preliminary ? 2004 microchip technology inc. register 12-1: ansel0 ? analog select register (address: 91h) register 12-2: ansel1 ? analog select register (address: 93h) table 12-2: analog select cross reference r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 bit 7 bit 0 bit 7-0: ans<7:0> : analog select bits analog select between analog or digital function on pins an<7:0>, respectively. 1 = analog input. pin is assigned as analog input. (1) 0 = digital i/o. pin is assigned to port or special function. note 1: setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change, if available. the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin. port reads of pins configured assigned as analog inputs will read as ? 0 ?. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown u-0 u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ? ans11 ans10 ans9 ans8 bit 7 bit 0 bit 7-0: ans<11:8> : analog select bits analog select between analog or digital function on pins an<11:8>, respectively. 1 = analog input. pin is assigned as analog input. (1) 0 = digital i/o. pin is assigned to port or special function. note 1: setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change, if available. the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin. port reads of pins assigned as analog inputs will read as ? 0 ?. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown analog select ans11 ans10 ans9 ans8 ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 analog channel an11 an10 an9 an8 an7 an6 an5 an4 an3 an2 an1 an0 i/o pin rb5 rb4 rc7 rc6 rc3 rc2 rc1 rc0 ra4 ra2 ra1 ra0
? 2004 microchip technology inc. preliminary ds41249a-page 81 PIC16F785 register 12-3: adcon0 ? a/d control register (address: 1fh) register 12-4: adcon1 ? a/d control register 1 (address: 9fh) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm vcfg chs3 chs2 chs1 chs0 go/done adon bit 7 bit 0 bit 7 adfm: a/d result formed select bit 1 = right justified 0 = left justified bit 6 vcfg: voltage reference bit 1 = v ref pin 0 = v dd bit 5-2 chs<3:0>: analog channel select bits 0000 = channel 00 (an0) 0001 = channel 01 (an1) 0010 = channel 02 (an2) 0011 = channel 03 (an3) 0100 = channel 04 (an4) 0101 = channel 05 (an5) 0110 = channel 06 (an6) 0111 = channel 07 (an7) 1000 = channel 08 (an8) 1001 = channel 09 (an9) 1010 = channel 10 (an10) 1011 = channel 11 (an11) 1100 =cv ref 1101 =vr 1110 = reserved. do not use. 1111 = reserved. do not use. bit 1 go/done : a/d conversion status bit 1 = a/d conversion cycle in progress. setting this bit starts an a/d conversion cycle. this bit is automatically cleared by hardware when the a/d conversion has completed. 0 = a/d conversion completed/not in progress bit 0 adon: a/d conversion status bit 1 = a/d converter module is operating 0 = a/d converter is shut-off and consumes no operating current legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? adcs2 adcs1 adcs0 ? ? ? ? bit 7 bit 0 bit 7: unimplemented: read as ? 0 ? bit 6-4: adcs<2:0>: a/d conversion clock select bits 000 =f osc /2 001 =f osc /8 010 =f osc /32 x11 =f rc (clock derived from a dedicated internal oscillator = 500 khz max) 100 =f osc /4 101 =f osc /16 110 =f osc /64 bit 3-0: unimplemented: read as ? 0 ? legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC16F785 ds41249a-page 82 preliminary ? 2004 microchip technology inc. 12.1.7 configuring the a/d after the a/d module has been configured as desired, the selected channel must be acquired before the conversion is started. the analog input channels must have their corresponding tris bits selected as inputs. to determine sample time, see section 18.0 ?electri- cal specifications? . after this sample time has elapsed the a/d conversion can be started. these steps should be followed for an a/d conversion: 1. configure the a/d module: configure analog/digital i/o (ansx) configure voltage reference (adcon0) select a/d input channel (adcon0) select a/d conversion clock (adcon1) turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): clear adif bit (pir1<6>) set adie bit (pie1<6>) set peie and gie bits (intcon<7:6>) 3. wait the required acquisition time. 4. start conversion: set go/done bit (adcon0<1>) 5. wait for a/d conversion to complete, by either: polling for the go/done bit to be cleared (with interrupts disabled); or waiting for the a/d interrupt 6. read a/d result register pair (adresh:adresl), clear bit adif if required. 7. for next conversion, go to step 1 or step 2 as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2 t ad is required before the next acquisition starts. example 12-1: a/d conversion ;this code block configures the a/d ;for polling, vdd reference, r/c clock ;and ra0 input. ; ;conversion start & wait for complete ;polling code included. ; bcf status,rp1 ;bank 1 bsf status,rp0 ; movlw b?01110000? ;a/d rc clock movwf adcon1 bsf trisa,0 ;set ra0 to input bsf ansel0,0 ;set ra0 to analog bcf status,rp0 ;bank 0 movlw b?10000001? ;right, vdd vref, an0 movwf adcon0 call sampletime ;wait min sample time bsf adcon0,go ;start conversion btfsc adcon0,go ;is conversion done? goto $-1 ;no, test again movf adresh,w ;read upper 2 bits movwf resulthi bsf status,rp0 ;bank 1 movf adresl,w ;read lower 8 bits bcf status,rp0 ;bank 0 movwf resultlo
? 2004 microchip technology inc. preliminary ds41249a-page 83 PIC16F785 12.2 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 12-4. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), see figure 12-4. the maximum recom- mended impedance for analog sources is 10 k ? . as the impedance is decreased, the acquisition time may be decreased. after the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 12-1 may be used. this equation assumes that 1/2 lsb error is used (1024 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. to calculate the minimum acquisition time, t acq , see the picmicro ? mid-range reference manual (ds33023). equation 12-1: acquisition time example note 1: the reference voltage (v ref ) has no effect on the equation, since it cancels itself out. 2: the charge holding capacitor (c hold ) is not discharged after each conversion. 3: the maximum recommended impedance for analog sources is 10 k ? . this is required to meet the pin leakage specification. t acq amplifier settling time hold capacitor charging time temperature coefficient ++ = t amp t c t coff ++ = 2s t c temperature - 25c () 0.05s/c () [] ++ = t c c hold r ic r ss r s ++ () ln(1/2047) ? = 10pf 1k ? 7k ? 10k ? ++ () ? ln(0.0004885) = 1.37 = s t acq 2 s 1.37 s 50c- 25c () 0.05 s /c () [] ++ = 4.67 s = v applied 1e tc ? rc --------- ? ?? ?? ?? v applied 1 1 2047 ----------- - ? ?? ?? = v applied 1 1 2047 ----------- - ? ?? ?? v chold = v applied 1e t c ? rc --------- - ? ?? ?? ?? v chold = ;[1] v chold charged to within 1/2 lsb ;[2] v chold charge response to v applied ;combining [1] and [2] where c hold is charged to within 1/2 lsb: solving for t c : therefore:
PIC16F785 ds41249a-page 84 preliminary ? 2004 microchip technology inc. figure 12-4: analog input model c pin va r s anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = dac capacitance v ss 6v sampling switch 5v 4v 3v 2v 567891011 (k ? ) v dd = 10 pf 500 na legend c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions r ss
? 2004 microchip technology inc. preliminary ds41249a-page 85 PIC16F785 12.3 a/d operation during sleep the a/d converter module can operate during sleep. this requires the a/d clock source to be set to the f rc option. when the rc clock source is selected, the a/d waits one instruction before starting the conversion. this allows the sleep instruction to be executed, thus eliminating much of the switching noise from the con- version. when the conversion is complete, the go/done bit is cleared and the result is loaded into the adresh:adresl registers. if the a/d interrupt is enabled, the device awakens from sleep. if the gie bit (intcon<7>) is set, the program counter is set to the interrupt vector (0004h). if gie is clear, the next instruc- tion is executed. if the a/d interrupt is not enabled, the a/d module is turned off, although the adon bit remains set. when the a/d clock source is something other than rc, a sleep instruction causes the present conversion to be aborted and the a/d module is turned off. the adon bit remains set. figure 12-5: a/d transfer function 3ffh 3feh a/d output code 3fdh 3fch 004h 003h 002h 001h 000h full-scale 3fbh 1 lsb ideal 0v zero-scale transition v ref transition 1 lsb ideal full-scale range analog input voltage
PIC16F785 ds41249a-page 86 preliminary ? 2004 microchip technology inc. 12.4 effects of reset a device reset forces all registers to their reset state. thus, the a/d module is turned off and any pending conversion is aborted. the adresh:adresl regis- ters are unchanged. 12.5 use of the ccp trigger an a/d conversion can be started by the ?special event trigger? of the ccp module. this requires that the ccp1m3:ccp1m0 bits (ccp1con<3:0>) be pro- grammed as ? 1011 ? and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, starting the a/d conversion and the timer1 counter will be reset to zero. timer1 is reset to automatically repeat the a/d acquisition period with minimal software overhead (moving the adresh:adresl to the desired location). the appropriate analog input channel must be selected and the minimum acquisition done before the ?special event trigger? sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), then the ?special event trigger? will be ignored by the a/d module, but will still reset the timer1 counter. see section 8.0 ?capture/compare/pwm (ccp) mod- ule? for more information. table 12-3: summary of a/d registers addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets 05h, 105h porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --xx xxxx --uu uuuu 06h, 106h portb rb7 rb6 rb5 rb4 ? ? ? ? xxxx ---- uuuu ---- 07h, 107h portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu 0bh, 8bh intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 0ch pir1 eeif adif ccp1if c2if c1if osfif tmr2if tmr1if 0000 0000 0000 0000 1eh adresh most significant 8 bits of the left justified a/d result or 2 bits of the right justified result xxxx xxxx uuuu uuuu 1fh adcon0 adfm vcfg chs3 chs2 chs1 chs0 go/done adon 0000 0000 0000 0000 85h, 185h trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 --11 1111 86h, 186h trisb trisb7 trisb6 trisb5 trisb4 ? ? ? ? 1111 ---- 1111 ---- 87h, 187h trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 8ch pie1 eeie adie ccp1ie c2ie c1ie osfie tmr2ie tmr1ie 0000 0000 0000 0000 91h ansel0 ans7 ans6 ans5 ans4 ans3 ans2 ans1 ans0 1111 1111 1111 1111 93h ansel1 ? ? ? ? ans11 ans10 ans9 ans8 ---- 1111 ---- 1111 9eh adresl least significant 2 bits of the left justified a/d result or 8 bits of the right justified result xxxx xxxx uuuu uuuu 9fh adcon1 ? adcs2 adcs1 adcs0 ? ? ? ? -000 ---- -000 ---- legend: x = unknown, u = unchanged, ? = unimplemented read as ' 0 '. shaded cells are not used for a/d module.
? 2004 microchip technology inc. preliminary ds41249a-page 87 PIC16F785 13.0 two-phase pwm the two-phase pwm (pulse width modulator) is a stand-alone peripheral that supports: single or dual-phase pwm single complementary output pwm with overlap/ delay sync input/output to cascade devices for addi- tional phases setting either, or both, of the ph1en or ph2en bits of the pwmcon0 register will activate the pwm module (see register 13-1). if ph1 is used then trisc<1> must be cleared to configure the pin as an output. the same is true for trisc<4> when using ph2. 13.1 pwm period the pwm period is derived from the main clock (f osc ), the pwm prescaler and the period counter (see figure 13-3). the prescale bits (pwmp<1:0>, see register 13-2) determine the value of the clock divider which divides the system clock (f osc ) to the pwm_clk. this pwm_clk is used to drive the pwm counter. in master mode, the pwm counter is reset when the count reaches the period count (per<4:0>, see register 13-2), which determines the frequency of the pwm. the relationship between the pwm frequency, prescale and period count is shown in equation 13-1. equation 13-1: pwm frequency the maximum pwm frequency is f osc /2, since the period count must be greater than zero. in slave mode, the period counter is reset by the sync input, which is the master device period counter reset. for proper operation, the slave period count should be equal to or greater than that of the master. 13.2 pwm phase each enabled phase output is driven active when the phase counter matches the corresponding pwm phase count (ph<4:0>, see register 13-4 and register 13-5). the phase output remains true until terminated by a feedback signal from either of the comparators or the auto shutdown activates. phase granularity is a function of the period count value. for example, if per<4:0> = 3, each output can be shifted in 90 steps (see equation 13-2) . equation 13-2: phase resolution 13.3 pwm duty cycle each pwm output is driven inactive, terminating the drive period, by asynchronous feedback through the internal comparators. the duty cycle resolution is in effect infinitely adjustable. either or both comparators can be used to reset the pwm by setting the corre- sponding comparator enable bit (cxen, see register 13-3). duty cycles of 100% can be obtained by suppressing the feedback which would otherwise terminate the pulse. the comparator outputs can be ?held off?, or blanked, by enabling the corresponding blank bit (blankx, see register 13-1) for each phase. the blank bit disables the comparator outputs for 1/2 of a system clock (f osc ), thus ensuring at least tosc/2 active time for the pwm output. blanking avoids early termination of the pwm output which may result due to switching transients at the beginning of the cycle. 13.4 master/slave operation multiple chips can operate together to achieve addi- tional phases by operating one as the master and the others as slaves. when the pwm is configured as a master, the rb7/sync pin is an output and generates a high output for one pwm_clk period at the end of each pwm period (see figure 13-4). when the pwm is configured as a slave, the rb7/ sync pin is an input. the high input from a master in this configuration resets the pwm period counter which synchronizes the slave unit at the end of each pwm period. proper operation of a slave device requires a common external f osc clock source to drive the master and slave. the pwm prescale value of the slave device must also be identical to that of the master. as mentioned previously, the slave period count value must be greater than or equal to that of the master. the pwm counter will be reset and held at zero when both ph1en and ph2en (pwmcon0<1:0>) are false. if the pwm is configured as a slave, the pwm counter will remain reset at zero until the first sync input is received. pwm freq fosc 2 pwmp per 1 + () ? () --------------------------------------------------- - = phase deg 360 per 1 + () ------------------------- =
PIC16F785 ds41249a-page 88 preliminary ? 2004 microchip technology inc. 13.5 active pwm output level the pwm output signal can be made active high or low by setting or resetting the corresponding pol bit (see register 13-3 and register 13-4). when pol is ? 1 ? the active output state is v ol . when pol is ? 0 ? the active output state is v oh . 13.6 auto-shutdown and auto-restart when the pwm is enabled, the pwm outputs may be configured for auto-shutdown by setting the pasen bit (see register 13-1). v il on the ra2/an2/t0cki/int/ c1out pin will cause a shutdown event if auto-shut- down is enabled. an auto-shutdown event immedi- ately places the pwm outputs in the inactive state (see section 13.5 ?active pwm output level? ) and the pwm phase and period counters are reset and held to zero. the pwmase bit (see register 13-2) is set by hard- ware when a shutdown event occurs. if automatic restarts are not enabled (prsen = 0 , see register 13-1), pwm operation will not resume until the pwmase bit is cleared by firmware after the shut- down condition clears. the pwmase bit can not be cleared as long as the shutdown condition exists. if automatic restarts are not enabled, the auto-shutdown mode can be forced by writing a ? 1 ? to the pwmase bit. if automatic restarts are enabled (prsen = 1 ), the pwmase bit is automatically cleared and pwm oper- ation resumes when the auto-shutdown event clears (v ih on the ra2/an2/t0cki/int/c1out pin). figure 13-3: 2 phase pwm simplified block diagram prescale pwmph1 pwmph1 pwmph1 pwmph1<4:0> phase counter f osc sync ph1 c1out c2out pwmp<1:0> per<4:0> pwm_clk 5 pwm_count pha1 1,2,4,8 0 1 s r* pwmase master m s res q pwmase blank1 pwmph2 pwmph2 pwmph2 pwmph2<4:0> ph2 pha2 s r* q pwmase blank2 *reset dominant *reset dominant ph1en ph2en ph1en ph2en
? 2004 microchip technology inc. preliminary ds41249a-page 89 PIC16F785 register 13-1: pwm control register 0 (pwmcon0: 111h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 prsen pasen blank2 blank1 sync1 sync0 ph2en ph1en bit 7 bit 0 bit 7 prsen: pwm restart enable bit 1 = upon auto-shutdown, the pwmase shutdown bit clears automatically once the shutdown condition goes away. the pwm restarts automatically 0 = upon auto-shutdown, the pwmase must be cleared in firmware to restart the pwm. bit 6 pasen: pwm auto-shutdown enable bit 0 = pwm auto-shutdown is disabled 1 =v il on int pin will cause auto-shutdown event bit 5 blank2: ph2 blanking bit 1 = the ph2 pin is active for a minimum of 1/2 of an f osc clock period after it is set 0 = the ph2 pin is reset as soon as the comparator trigger is active bit 4 blank1: ph1 blanking bit 1 = the ph1 pin is active for a minimum of 1/2 of an f osc clock period after it is set 0 = the ph1 pin is reset as soon as the comparator trigger is active bit 3-2 sync<1:0>: sync pin function bits 0x = sync pin not used for pwm. pwm acts as its own master. rb6/sync pin is available for general purpose i/o. 10 = sync pin acts as system slave, receiving the pwm counter reset pulse 11 = sync pin acts as system master, driving the pwm counter reset pulse bit 1 ph2en: ph2 pin enabled 1 = the ph2 pin is driven by the pwm signal 0 = the ph2 pin is not used for pwm functions bit 0 ph1en: ph1 pin enabled 1 = the ph1 pin is driven by the pwm signal 0 = the ph1 pin is not used for pwm functions legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC16F785 ds41249a-page 90 preliminary ? 2004 microchip technology inc. register 13-2: pwm clock control register (p wmclk: 112h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pwmase pwmp1 pwmp0 per4 per3 per2 per1 per0 bit 7 bit 0 bit 7 pwmase: pwm auto-shutdown event status bit 0 = pwm outputs are operating. 1 = a shutdown event has occured. pwm outputs are inactive. bit 6-5 pwmp<1:0>: pwm clock prescaler bits 00 = pwm clock = f osc 1 01 = pwm clock = f osc 2 10 = pwm clock = f osc 4 11 = pwm clock = f osc 8 bit 4-0 per<4:0>: pwm period bits 00000 = not used. (period = pwm clock 1) 00001 = period = pwm clock 2 0.... = . . . 01111 = period = pwm clock 16 10000 = period = pwm clock 17 1.... = . . . 11110 = period = pwm clock 31 11111 = period = pwm clock 32 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds41249a-page 91 PIC16F785 register 13-3: pwm phase 1 control register (pwmph1: 113h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pol c2en c1en ph4 ph3 ph2 ph1 ph0 bit 7 bit 0 bit 7 pol: ph1 output polarity bit 1 = ph1 pin is active low 0 = ph1 pin is active high bit 6 c2en: comparator 2 enable bit 1 = ph1 is reset when c2out is high 0 = ph1 ignores comparator 2 bit 5 c1en: comparator1 enable bit 1 = ph1 is reset when c1out is high 0 = ph1 ignores comparator 1 bit 4-0 ph<4:0>: pwm phase bits 00000 = ph1 is synchronous with the pwm sync pulse 00001 = ph1 is delayed by 1 pwm_clk pulse ..... = . . . 11111 = ph1 is delayed by 31 pwm_clk pulses legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC16F785 ds41249a-page 92 preliminary ? 2004 microchip technology inc. register 13-4: pwm phase 2 control register (pwmph2: 114h) figure 13-4: 2 phase pwm system timing r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pol c2en c1en ph4 ph3 ph2 ph1 ph0 bit 7 bit 0 bit 7 pol: ph2 output polarity bit 1 = ph2 pin is active low 0 = ph2 pin is active high bit 6 c2en: comparator 2 enable bit 1 = ph2 is reset when c2out is high 0 = ph2 ignores comparator 2 bit 5 c1en: comparator1 enable bit 1 = ph2 is reset when c1out is high 0 = ph2 ignores comparator 1 bit 4-0 ph<4:0>: pwm phase bits 00000 = ph2 is synchronous with the pwm sync pulse 00001 = ph2 is delayed by 1 pwm clock pulse ..... = . . . 11111 = ph2 is delayed by 31 pwm clock pulse legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown 0123 0123 0123 01 f osc sync pwm_count pwm_clk c1out c2out pha1 pha2 phase 1 setup: ph<4:0> = 0x00, c1en = 1, blank1 = 0 phase2 setup: ph<4:0> = 0x02, c2en = 1, blank2 = 1 pwmp<1:0>=0 x 01, per<4:0>=0 x 03 3
? 2004 microchip technology inc. preliminary ds41249a-page 93 PIC16F785 figure 13-5: 2 phase pwm auto-shutdown and sync timing figure 13-6: 2 phase pwm start up timing 01 2 012 3012 30 f osc sync pwm_count pwm_clk shutdown pha1 pha2 phase1 setup: ph<4:0> = 0x00, c1en = 1, blank1 = 0 phase2 setup: ph<4:0> = 0x02, c2en = 1, blank2 = 1 pwmp<1:0> = 0 x 01, per<4:0> = 0 x 03 pwm_clk 01 2 012 3 012 pwm_count 3 0 master slave 012 301 f osc sync pwm_count pwm_clk phnen phnen pwmp<1:0> = 0 x 01, per<4:0> = 0 x 03 pwm_clk 012 3 012 pwm_count 3 master slave 0 2
PIC16F785 ds41249a-page 94 preliminary ? 2004 microchip technology inc. 13.7 example single phase application figure 13-7 shows an example of a single phase buck voltage regulator application. the pwm output drives q1 with pulses to alternately charge and discharge l1. c4 holds the charge from l1 during the inactive cycle of the drive period. r4 and c3 form a ramp generator. at the beginning of the pwm period, the pwm output goes high causing the voltage on c3 to rise concur- rently with the current in l1. when the voltage across c3 reaches the threshold level present at the positive input of comparator 1, the comparator output changes and terminates the drive output from the pwm to q1. when q1 is not driven, the current path to l1 through q1 is interrupted, but since the current in l1 cannot stop instantly, the current continues to flow through d2 as l1 discharges into c4. d1 quickly discharges c3 in preparation of the next ramp cycle. resistor divider r5 and r6 scale the output voltage, which is inverted and amplified by op amp 1 relative to the reference voltage present at the non-inverting pin of the op amp. r3, c5 and c2 form the inverting stabiliza- tion gain feedback of the amplifier. the vr reference supplies a stable reference to the non-inverting input of the op amp, which is tweaked by the voltage source created by a secondary time based pwm output of the ccp and r1 and c1. output regulation occurs by the following principle: if the regulator output voltage is too low, then the voltage to the non-inverting input of comparator 1 will rise, resulting in a higher threshold voltage and conse- quently longer pwm drive pulses into q1. if the output voltage is too high, then the voltage to the non-inverting input of comparator 1 will fall, resulting in shorter pwm drive pulses into q1. figure 13-7: example single phase application v unreg c1 opa1 ccp vr PIC16F785 fet driver f osc r1 r2 c1 r3 c2 r4 d1 d2 l1 q1 c3 c4 r5 r6 c5 2 phase pwm ph1
? 2004 microchip technology inc. preliminary ds41249a-page 95 PIC16F785 13.8 complementary output mode the 2 phase pwm module may be configured to oper- ate in a complementary output mode where ph1 and ph2 are always 180 degrees out-of-phase (see figure 13-8). three complementary modes are avail- able and are selected by the comod<1:0> bits in the pwmcon1 register (see register 13-5). the differ- ence between the modes is the method by which the ph1 and ph2 outputs switch from the active to the inactive state during the pwm period. the complementary output mode facilitates driving series connected mosfet drivers by providing over- lap or deadband drive timing between each phase out- put (see figure 13-9). overlap or deadband times are selectable by the cmdly<4:0> bits of the pwmcon1 register. delays from 0 to 155 nanoseconds (typical) with a resolution of 5 nanoseconds (typical) are avail- able. selection between overlap or deadband delay is con- trolled by the ovrlp bit of the pwm control register (pwmcon1<7>). register 13-5: pwm control register 1 (pwmcon1: 110h) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ovrlpcomod1comod0cmdly4cmdly3cmdly2cmdly1cmdly0 bit 7 bit 0 bit 7 ovrlp: delay overlap select bit 1 = delay time is overlap time between ph1 and ph2 0 = delay time is deadtime between ph1 and ph2 bit 6-5 comod<1:0>: complementary mode select bits 00 = normal 2 phase operation. complementary mode is disabled. 01 = complementary operation. on time is terminated by c1out or c2out. 10 = complementary operation. on time is terminated by pwmph2<4:0>=pwm_count. 11 = complementary operation. on time is terminated by pwmph2<4:0>=pwm_count or c1out or c2out. bit 4-0 cmdly<4:0>: typical complementary drive deadtime/overlap time. 00000 = delay = 0. 00001 = delay = 5 ns 00010 = delay = 10 ns ..... = . . . 11111 = delay = 155 ns legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC16F785 ds41249a-page 96 preliminary ? 2004 microchip technology inc. figure 13-8: complementary output pwm block diagram figure 13-9: complementary output pwm timing prescale pwmph1 pwmph1 pwmph2<4:0> pwmph2 pwmph1 pwmph1<4:0> phase count f osc sync ph1 ph2 c1out c2out ps<1:0> per<4:0> pwm_clk 5 pwm_count pwmase pha1 pha2 shutdown delay 1 0 1 0 s r q 01 10 delay 1 0 1 0 s r q comod<1:0> ovrlp cmdly<4:0> 5 5 11 0123 0123 0123 01 f osc sync pwm_count pwm_clk c1out pha1 pha2 phase 1 setup: ph<4:0> = 0x00, c1en = 1, blank1 = 0, comod<1:0> = 0x01 pwmp<1:0> = 0 x 01, per<4:0> = 0 x 03 3 delay delay delay delay ovrlp = 0 ovrlp = 1
? 2004 microchip technology inc. preliminary ds41249a-page 97 PIC16F785 table 13-1: registers/bits associated with pwm addressname bit 7bit 6bit 5bit 4bit 3bit 2 bit 1bit 0 value on: por, bor value on all other resets 98h refcon ? ? bgst vrbb vren vroe cvroe ? --00 000- --00 000- 99h vrcon c1vren c2vren vrr ? vr3 vr2 vr1 vr0 000- 0000 000- 0000 119h cm1con0 c1on c1out c1oe c1pol c1sp c1r c1ch1 c1ch0 0000 0000 0000 0000 11ah cm2con0 c2on c2out c2oe c2pol c2sp c2r c2ch1 c2ch0 0000 0000 0000 0000 110h pwmcon1 ovrlp comod1 comod0 cmdly4 cmdly3 cmdly2 cmdly1 cmdly0 0000 0000 0000 0000 111h pwmcon0 prsen pasen blank2 blank1 sync1 sync0 ph2en ph1en 0000 0000 0000 0000 112h pwmclk pwmase pwmp1 pwmp0 per4 per3 per2 per1 per0 0000 0000 0000 0000 113h pwmph1 pol c2en c1en ph4 ph3 ph2 ph1 ph0 0000 0000 0000 0000 114h pwmph2 pol c2en c1en ph4 ph3 ph2 ph1 ph0 0000 0000 0000 0000 legend: x = unknown, u = unchanged, ? = unimplemented read as ? 0 ?, q = value depends upon condition. shaded cells are not used by data pwm module.
PIC16F785 ds41249a-page 98 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds41249a-page 99 PIC16F785 14.0 data eeprom memory the eeprom data memory is readable and writable during normal operation (full v dd range). this memory is not directly mapped in the register file space. instead, it is indirectly addressed through the special function registers. there are four sfrs used to read and write this memory: eecon1 eecon2 (not a physically implemented register) eedat eeadr eedat holds the 8-bit data for read/write, and eeadr holds the address of the eeprom location being accessed. the PIC16F785 has 256 bytes of data eeprom with an address range from 0h to ffh. the eeprom data memory allows byte read and write. a byte write automatically erases the location and writes the new data (erase before write). the eeprom data memory is rated for high erase/write cycles. the write time is controlled by an on-chip timer. the write time will vary with voltage and temperature, as well as from chip-to-chip. please refer to ac specifications in section 18.0 ?electrical specifications? for exact limits. when the data memory is code-protected, the cpu may continue to read and write the data eeprom memory. the device programmer can no longer access the data eeprom data and will read zeroes. additional information on the data eeprom is available in the picmicro ? mid-range reference man- ual , (ds33023). register 14-1: eedat ? eeprom data register (address: 9ah) register 14-2: eeadr ? eeprom address register (address: 9bh) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eedat7 eedat6 eedat5 eedat4 eedat3 eedat2 eedat1 eedat0 bit 7 bit 0 bit 7-0 eedatn : byte value to write to or read from data eeprom bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eeadr7 eeadr6 eeadr5 eeadr4 eeadr3 eeadr2 eeadr1 eeadr0 bit 7 bit 0 bit 7-0 eeadr : specifies one of 256 locations for eeprom read/write operation bits legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
PIC16F785 ds41249a-page 100 preliminary ? 2004 microchip technology inc. 14.1 eecon1 and eecon2 registers eecon1 is the control register with four low-order bits physically implemented. the upper four bits are non- implemented and read as ? 0 ?s. control bits rd and wr initiate read and write, respectively. these bits cannot be cleared, only set in software. they are cleared in hardware at completion of the read or write operation. the inability to clear the wr bit in software prevents the accidental, premature termination of a write operation. the wren bit, when set, will allow a write operation. on power-up, the wren bit is clear. the wrerr bit is set when a write operation is interrupted by a mclr reset, or a wdt time-out reset during normal operation. in these situations, following reset, the user can check the wrerr bit, clear it and rewrite the loca- tion. the eedat and eeadr registers are cleared by a reset. therefore, the eedat and eeadr registers will need to be re-initialized. interrupt flag eeif bit (pir1<7>) is set when write is complete. this bit must be cleared in software. eecon2 is not a physical register. reading eecon2 will read all ? 0 ?s. the eecon2 register is used exclusively in the data eeprom write sequence. register 14-3: eecon1 ? eeprom control regist er (address: 9ch) note: the eecon1, eedat and eeadr registers should not be modified during a data eeprom write (wr bit = ? 1 ?). u-0 u-0 u-0 u-0 r/w-x r/w-0 r/s-0 r/s-0 ? ? ? ? wrerr wren wr rd bit 7 bit 0 bit 7-4 unimplemented: read as ? 0 ? bit 3 wrerr: eeprom error flag bit 1 = a write operation is prematurely terminated (any mclr reset, any wdt reset during normal operation or bor reset) 0 = the write operation completed bit 2 wren: eeprom write enable bit 1 = allows write cycles 0 = inhibits write to the data eeprom bit 1 wr: write control bit 1 = initiates a write cycle (the bit is cleared by hardware once write is complete. the wr bit can only be set, not cleared, in software.) 0 = write cycle to the data eeprom is complete bit 0 rd: read control bit 1 = initiates an eeprom read (read takes one cycle. rd is cleared in hardware. the rd bit can only be set, not cleared, in software.) 0 = does not initiate an eeprom read legend: s = bit can only be set r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown
? 2004 microchip technology inc. preliminary ds41249a-page 101 PIC16F785 14.2 reading the eeprom data memory to read a data memory location, the user must write the address to the eeadr register and then set control bit rd (eecon1<0>), as shown in example 14-1. the data is available, in the very next cycle, in the eedat register. therefore, it can be read in the next instruction. eedat holds this value until another read, or until it is written to by the user (during a write operation). example 14-1: data eeprom read 14.3 writing to the eeprom data memory to write an eeprom data location, the user must first write the address to the eeadr register and the data to the eedat register. then the user must follow a specific sequence to initiate the write for each byte, as shown in example 14-2. example 14-2: data eeprom write the write will not initiate if the above sequence is not followed exactly (write 55h to eecon2, write aah to eecon2, then set wr bit) for each byte. we strongly recommend that interrupts be disabled during this code segment. a cycle count is executed during the required sequence. any number that is not equal to the required cycles to execute the required sequence will prevent the data from being written into the eeprom. additionally, the wren bit in eecon1 must be set to enable write. this mechanism prevents accidental writes to data eeprom due to errant (unexpected) code execution (i.e., lost programs). the user should keep the wren bit clear at all times, except when updating the eeprom. the wren bit is not cleared by hardware. after a write sequence has been initiated, clearing the wren bit will not affect this write cycle. the wr bit will be inhibited from being set unless the wren bit is set. at the completion of the write cycle, the wr bit is cleared in hardware and the ee write complete interrupt flag bit (eeif) is set. the user can either enable this interrupt or poll this bit. the eeif bit (pir1<7>) register must be cleared by software. 14.4 write verify depending on the application, good programming practice may dictate that the value written to the data eeprom should be verified (see example 14-3) to the desired value to be written. example 14-3: write verify 14.4.1 using the data eeprom the data eeprom is a high-endurance, byte address- able array that has been optimized for the storage of frequently changing information (e.g., program variables or other data that are updated often). when variables in one section change frequently, while vari- ables in another section do not change, it is possible to exceed the total number of write cycles to the eeprom (specification d124) without excceding the total number of write cycles to a single byte (specifica- tions d120 and d120a). if this is the case, then an array refresh must be performed. for this reason, vari- ables that change infrequently (such as constants, ids, calibration, etc.) should be stored in flash program memory. 14.5 protection against spurious write there are conditions when the user may not want to write to the data eeprom memory. to protect against spurious eeprom writes, various mechanisms have been built in. on power-up, wren is cleared. also, the power-up timer (64 ms duration) prevents eeprom write. the write initiate sequence and the wren bit together help prevent an accidental write during: brown-out power glitch software malfunction bsf status,rp0 ;bank 1 bsf status,rp1 movlw config_addr ; movwf eeadr ;address to read bsf eecon1,rd ;ee read movf eedat,w ;move data to w bsf status,rp0 ;bank 1 bsf status,rp1 bsf eecon1,wren ;enable write bcf intcon,gie ;disable ints movlw 55h ;unlock write movwf eecon2 ; movlw aah ; movwf eecon2 ; bsf eecon1,wr ;start the write bsf intcon,gie ;enable ints sequence required bsf status,rp0 ;bank 1 bsf status,rp1 movf eedat,w ;eedat not changed ; from previous write bsf eecon1,rd ;yes, read the ; value written xorwf eedat,w btfss status,z ;is data the same goto write_err ;no, handle error ;yes, continue
PIC16F785 ds41249a-page 102 preliminary ? 2004 microchip technology inc. 14.6 data eeprom operation during code-protect data memory can be code-protected by programming the cpd bit in the configuration word (register 15-1) to ? 0 ?. when the data memory is code-protected, the cpu is able to read and write data to the data eeprom. it is recommended to code-protect the program memory when code-protecting data memory. this prevents anyone from programming zeroes over the existing code (which will execute as nop s) to reach an added routine, programmed in unused program memory, which outputs the contents of data memory. programming unused locations in program memory to ? 0 ? will also help prevent data memory code protection from becoming breached. table 14-1: registers/bits associated with data eeprom addressname bit 7bit 6bit 5bit 4bit 3bit 2 bit 1bit 0 value on: por, bor value on all other resets 0bh, 8bh intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 0ch pir1 eeif adif ccp1if c2if c1if osfif tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 eeie adie ccp1ie c2ie c1ie osfie tmr2ie tmr1ie 0000 0000 0000 0000 9ah eedat eedat7 eedat6 eedat5 eedat4 eedat3 eedat2 eedat1 eedat0 0000 0000 0000 0000 9bh eeadr eeadr7 eeadr6 eeadr5 eeadr4 eeadr3 eeadr2 eeadr1 eeadr0 0000 0000 0000 0000 9ch eecon1 ? ? ? ? wrerr wren wr rd ---- x000 ---- q000 9dh eecon2 eeprom control register 2 (not a physical register) ---- ---- ---- ---- legend: x = unknown, u = unchanged, ? = unimplemented read as ? 0 ?, q = value depends upon condition. shaded cells are not used by data eeprom module.
? 2004 microchip technology inc. preliminary ds41249a-page 103 PIC16F785 15.0 special features of the cpu the PIC16F785 has a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving features and offer code protection. these features are: reset - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) interrupts watchdog timer (wdt) oscillator selection sleep code protection id locations in-circuit serial programming? (iscp?) the PIC16F785 has two timers that offer necessary delays on power-up. one is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable. the other is the power- up timer (pwrt), which provides a fixed delay of 64 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. there is also circuitry to reset the device if a brown-out occurs, which can use the power-up timer to provide at least a 64 ms reset. with these three functions on- chip, most applications need no external reset circuitry. the sleep mode is designed to offer a very low current power-down mode. the user can wake-up from sleep through: external reset watchdog timer wake-up an interrupt several oscillator options are also made available to allow the part to fit the application. the intosc option saves system cost, while the lp crystal option saves power. a set of configuration bits are used to select various options (see register 15-1). 15.1 configuration bits the configuration bits can be programmed (read as ? 0 ?), or left unprogrammed (read as ' 1 ?) to select various device configurations as shown in register 15-1. these bits are mapped in program memory location 2007h. 15.2 calibration bits the brown-out reset (bor), power-on reset (por), 8 mhz internal oscillator (hfintosc), bandgap offset (bgoff) and bandgap temperature compensation (bgtmp) are factory calibrated and should not be altered. these calibration values are stored in five calibration words which are mapped in program memory locations 2008h and 2009h respectively. the calibration words are not erased when the device is erased when using the procedure described in the PIC16F785 memory programming specification (ds41237). therefore, it is not necessary to store and reprogram these values when the device is erased. note: address 2007h is beyond the user program memory space. it belongs to the special configuration memory space (2000h ? 3fffh), which can be accessed only during programming. see PIC16F785 memory programming specification (ds41237) for more information. note: addresses 2008h and 2009h are beyond the user program memory space. they belong to the special configuration memory space (2000h ? 3fffh), which can be accessed only during programming. see PIC16F785 memory programming speci- fication (ds41237) for more information.
PIC16F785 ds41249a-page 104 preliminary ? 2004 microchip technology inc. register 15-1: config ? co nfiguration word (address: 2007h) ? ? fcmen ieso boren1 boren0 cpd cp mclre pwrte wdte fosc2 fosc1 fosc0 bit 13 bit 0 bit 13-12 unimplemented : read as ? 1 ? bit 11 fcmen: fail clock monitor enabled bit 1 = fail-safe clock monitor is enabled 0 = fail-safe clock monitor is disabled bit 10 ieso: internal external switchover bit 1 = internal external switchover mode is enabled 0 = internal external switchover mode is disabled bit 9-8 boren<1:0>: brown-out reset selection bits (1) 11 = bor enabled 10 = bor enabled during operation and disabled in sleep 01 = bor controlled by sboren bit (pcon<4>) 00 = bor disabled bit 7 cpd : data code protection bit (2,3) 1 = data memory code protection is disabled 0 = data memory code protection is enabled bit 6 cp : code protection bit (2) 1 = program memory code protection is disabled 0 = program memory c ode protection is enabled bit 5 mclre: ra3/mclr pin function select bit (4) 1 = ra3/mclr pin function is mclr 0 = ra3/mclr pin function is digital input, mclr internally tied to v dd bit 4 pwrte : power-up timer enable bit 1 = pwrt disabled 0 = pwrt enabled bit 3 wdte: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled and can be enabled by swdten bit (wdtcon<0>) bit 2-0 fosc<2:0>: oscillator selection bits 111 = rc oscillator: clkout function on ra4/an3/t1 g/osc2/clkout pin, rc on ra5/t1cki/osc1/clkin 110 = rcio oscillator: i/o function on ra4/an3/t1g/osc2/clkout pin, rc on ra5/t1cki/osc1/clkin 101 = intosc oscillator: clkout function on ra4/an3/t1g/osc2/clkout pin, i/o function on ra5/t1cki/osc1/clkin 100 = intoscio oscillator: i/o function on ra4/an3/t1g/osc2/clkout pin, i/o function on ra5/t1cki/osc1/clkin 011 = ec: i/o function on ra4/an3/t1g/osc2/clkout pin, clkin on ra5/t1cki/osc1/clkin 010 = hs oscillator: high speed crystal/resonator on ra4/an3/t1g/osc2/clkout and ra5/t1cki/osc1/clkin 001 = xt oscillator: crystal/resonator on ra4/an3/t1g/osc2/clkout and ra5/t1cki/osc1/clkin 000 = lp oscillator: low power crystal on ra4/an3/t1g/osc2/clkout and ra5/t1cki/osc1/clkin note 1: enabling brown-out reset does not automatically enable power-up timer. 2: program memory bulk erase must be per formed to turned off code protection. 3: the entire data eeprom will be erased when the code protection is turned off. 4: when mclr is asserted in intosc or rc mode, the internal clock oscillator is disabled.
? 2004 microchip technology inc. preliminary ds41249a-page 105 PIC16F785 15.3 reset the PIC16F785 differentiates between various kinds of reset: a) power-on reset (por) b) wdt reset during normal operation c) wdt reset during sleep d) mclr reset during normal operation e) mclr reset during sleep f) brown-out reset (bor) some registers are not affected in any reset condition; their status is unknown on por and unchanged in any other reset. most other registers are reset to a ?reset state? on: power-on reset mclr reset mclr reset during sleep wdt reset brown-out reset (bor) they are not affected by a wdt wake-up since this is viewed as the resumption of normal operation. to and pd bits are set or cleared differently in different reset situations, as indicated in table 15-2. these bits are used in software to determine the nature of the reset. see table 15-4 for a full description of reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 15-1. the mclr reset path has a noise filter to detect and ignore small pulses. see section 18.0 ?electrical specifications? for pulse width specifications. figure 15-1: simplified block diagram of on-chip reset circuit s r q external reset mclr /v pp pin v dd osc1/ wdt module v dd rise detect ost/pwrt lfintosc wdt time-out power-on reset ost 10-bit ripple counter pwrt chip_reset 11-bit ripple counter reset enable ost enable pwrt sleep brown-out (1) reset sboren boren clki pin note 1: refer to the configuration word register (register 15-1).
PIC16F785 ds41249a-page 106 preliminary ? 2004 microchip technology inc. 15.3.1 power-on reset the on-chip por circuit holds the chip in reset until v dd has reached a high enough level for proper operation. to take advantage of the por, simply con- nect the mclr pin through a resistor to v dd . this will eliminate external rc components usually needed to create power-on reset. a minimum rise time for v dd is required. see section 18.0 ?electrical specifica- tions? for details. if the bor is enabled, the minimum rise time specification does not apply. the bor circuitry will keep the device in reset until v dd reaches v bor (see section 15.3.4 ?brown-out reset (bor)? ) the por circuit on this device has a por re-arm circuit. this circuit is designed to ensure a re-arm of the por circuit if v dd drops below a preset re-arming voltage (v parm ) for at least the minimum required time. once v dd has been below the re-arming point for the minimum required time, the por reset will reactivate and remain in reset until v dd returns to a value greater than v por. at this point, a 1 s (typical) delay will be initiated to allow v dd to continue to ramp to a voltage safely above v por. when the device starts normal operation (exits the reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operat- ing conditions are met. for additional information, refer to the ?power-up trouble shooting? application note (ds00607). 15.3.2 master clear (m clr ) PIC16F785 has a noise filter in the mclr reset path. the filter will detect and ignore small pulses. it should be noted that a wdt reset does not drive mclr pin low. the behavior of the esd protection on the mclr pin has been altered from early devices of this family. voltages applied to the pin that exceed its specification can result in both mclr resets and excessive current beyond the device specification during the esd event. for this reason, microchip recommends that the mclr pin no longer be tied directly to v dd . the use of an rc network, as shown in figure 15-2, is suggested. an internal mclr option is enabled by clearing the mclre bit in the configuration word. when cleared, mclr is internally tied to v dd and an internal weak pull-up is enabled for the mclr pin. in-circuit serial programming is not affected by selecting the internal mclr option. figure 15-2: recommended mclr circuit 15.3.3 power-up timer (pwrt) the power-up timer provides a fixed 64 ms (nominal) time out on power-up only, from por or brown-out reset. the power-up timer operates from the 31 khz lfintosc oscillator. for more information, see section 3.4 ?internal clock modes? . the chip is kept in reset as long as pwrt is active. the pwrt delay allows the v dd to rise to an acceptable level. a config- uration bit, pwrte can disable (if ? 1 ?) or enable (if ? 0 ?) the power-up timer. the power-up timer should be enabled when brown-out reset is enabled, although it is not required. the power-up time delay will vary from chip-to-chip and vary due to: v dd variation temperature variation process variation see dc parameters for details ( section 18.0 ?electrical specifications? ). v dd mclr r1 1k ? ( or greater) c1 0.1 f (optional, not critical) PIC16F785
? 2004 microchip technology inc. preliminary ds41249a-page 107 PIC16F785 15.3.4 brown-out reset (bor) the boren0 and boren1 bits in the configuration word select one of four bor modes. two modes have been added to allow software or hardware control of the bor enable. when boren<1:0> = 01 , the sboren bit (pcon<4>) enables/disables the bor allowing it to be controlled in software. by selecting boren<1:0>, the bor is automatically disabled in sleep to conserve power and enabled on wake-up. in this mode, the sboren bit is disabled. see register 15-1 for the configuration word definition. if v dd falls below v bor for greater than parameter (t bor ), see section 18.0 ?electrical specifica- tions? , the brown-out situation will reset the device. this will occur regardless of v dd slew rate. a reset is not assured if v dd falls below v bor for less than parameter (t bor ). on any reset (power-on, brown-out reset, watchdog, etc.), the chip will remain in reset until v dd rises above v bor (see figure 15-3). the power-up timer will now be invoked, if enabled, and will keep the chip in reset an additional 64 ms. if v dd drops below v bor while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be re-initialized. once v dd rises above v bor , the power-up timer will execute a 64 ms reset. 15.3.5 bor calibration the PIC16F785 stores the bor calibration values in fuses located in the calibration word (2008h). the calibration word is not erased when using the speci- fied bulk erase sequence in the PIC16F785 memory programming specification (ds41237) and thus, does not require reprogramming. figure 15-3: brown-out situations note: the power-up timer is enabled by the pwrte bit in the configuration word. note: address 2008h is beyond the user program memory space. it belongs to the special configuration memory space (2000h ? 3fffh), which can be accessed only during programming. see PIC16F785 memory programming specification (ds41237) for more information. 64 ms (1) v bor v dd internal reset v bor v dd internal reset 64 ms (1) <64 ms 64 ms (1) v bor v dd internal reset note 1: 64 ms delay only if pwrte bit is programmed to ? 0 ?.
PIC16F785 ds41249a-page 108 preliminary ? 2004 microchip technology inc. 15.3.6 time-out sequence on power-up, the time-out sequence is as follows: first, pwrt time out is invoked after por has expired, then ost is activated after the pwrt time out has expired. the total time out will vary based on oscillator configu- ration and pwrte bit status. for example, in ec mode with pwrte bit equal to ? 1 ? (pwrt disabled), there will be no time out at all. figure 15-4, figure 15-5 and figure 15-6 depict time-out sequences. the device can execute code from the intosc, while ost is active by enabling two-speed start-up or fail-safe monitor (see section 3.6.2 ?two-speed start-up sequence? and section 3.7 ?fail-safe clock monitor? ). since the time outs occur from the por pulse, if mclr is kept low long enough, the time outs will expire. then bringing mclr high will begin execution immediately (see figure 15-5). this is useful for testing purposes or to synchronize more than one PIC16F785 device operating in parallel. table 15-5 shows the reset conditions for some special registers, while table 15-4 shows the reset conditions for all the registers. 15.3.7 power control (pcon) register the power control register pcon (address 8eh) has two status bits to indicate what type of reset that last occurred. bit 0 is bor (brown-out reset). bor is unknown on power-on reset. it must then be set by the user and checked on subsequent resets to see if bor = 0 , indicating that a brown-out has occurred. the bor status bit is a ?don?t care? and is not necessarily predictable if the brown-out circuit is disabled (boren<1:0> = 00 in the configuration word). bit 1 is por (power-on reset). it is a ? 0 ? on power-on reset and unaffected otherwise. the user must write a ? 1 ? to this bit following a power-on reset. on a subsequent reset, if por is ? 0 ?, it will indicate that a power-on reset has occurred (i.e., v dd may have gone too low). for more information, see section 15.3.4 ?brown-out reset (bor)? . table 15-1: time out in various situations table 15-2: status/pcon bits and their significance table 15-3: summary of registers associated with brown-out oscillator configuration power-up brown-out reset wake-up from sleep pwrte = 0 pwrte = 1 pwrte = 0 pwrte = 1 xt, hs, lp t pwrt + 1024t osc 1024t osc t pwrt + 1024t osc 1024t osc 1024t osc rc, ec, intosc t pwrt ?t pwrt ?? por bo r to pd condition 0x11 power-on reset 1011 brown-out reset uu0u wdt reset uu00 wdt wake-up uuuu mclr reset during normal operation uu10 mclr reset during sleep legend: u = unchanged, x = unknown address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por, bor value on all other resets (1) 03h, 103h 83h, 183h status irp rp1 rpo to pd z dc c 0001 1xxx 000q quuu 8eh pcon ? ? ? sboren ? ?por bor ---1 --qq ---u --uu legend: u = unchanged, x = unknown, ? = unimplem ented bit, reads as ? 0 ?, q = value depends on condition. shaded cells are not used by bor. note 1: other (non power-up) resets include mclr reset and watchdog timer reset during normal operation.
? 2004 microchip technology inc. preliminary ds41249a-page 109 PIC16F785 figure 15-4: time-out sequence on power-up (delayed mclr ): case 1 figure 15-5: time-out sequence on power-up (delayed mclr ): case 2 figure 15-6: time-out sequence on power-up (mclr with v dd ) t pwrt t ost v dd mclr internal por pwrt time out ost time out internal reset v dd mclr internal por pwrt time out ost time out internal reset t pwrt t ost t pwrt t ost v dd mclr internal por pwrt time out ost time out internal reset
PIC16F785 ds41249a-page 110 preliminary ? 2004 microchip technology inc. table 15-4: initialization condition for registers register address power-on reset mclr reset wdt reset brown-out reset (1) wake-up from sleep through interrupt wake-up from sleep through wdt time out w? xxxx xxxx uuuu uuuu uuuu uuuu indf 00h/80h xxxx xxxx xxxx xxxx uuuu uuuu tmr0 01h xxxx xxxx uuuu uuuu uuuu uuuu pcl 02h/82h 0000 0000 0000 0000 pc + 1 (3) status 03h/83h 0001 1xxx 000q quuu (4) uuuq quuu (4) fsr 04h/84h xxxx xxxx uuuu uuuu uuuu uuuu porta 05h --x0 x000 (6) --0u 0uuu (7) --uu uuuu portb 06h xx00 ---- (6) 00uu ---- (7) uuuu ---- portc 07h 00xx 0000 (6) uu00 uuuu (7) uuuu uuuu pclath 0ah/8ah ---0 0000 ---0 0000 ---u uuuu intcon 0bh/8bh 0000 0000 0000 0000 uuuu uuuu (2) pir1 0ch 0000 0000 0000 0000 uuuu uuuu (2) tmr1l 0eh xxxx xxxx uuuu uuuu uuuu uuuu tmr1h 0fh xxxx xxxx uuuu uuuu uuuu uuuu t1con 10h 0000 0000 uuuu uuuu uuuu uuuu tmr2 11h 0000 0000 0000 0000 uuuu uuuu t2con 12h -000 0000 -000 0000 -uuu uuuu ccpr1l 13h xxxx xxxx uuuu uuuu uuuu uuuu ccpr1h 14h xxxx xxxx uuuu uuuu uuuu uuuu ccp1con 15h --00 0000 --00 0000 --uu uuuu wdtcon 18h ---0 1000 ---0 1000 ---u uuuu adresh 1eh xxxx xxxx uuuu uuuu uuuu uuuu adcon0 1fh 0000 0000 0000 0000 uuuu uuuu option_reg 81h 1111 1111 1111 1111 uuuu uuuu trisa 85h --11 1111 --11 1111 --uu uuuu trisb 86h 1111 ---- 1111 ---- uuuu ---- trisc 87h 1111 1111 1111 1111 uuuu uuuu pie1 8ch 0000 0000 0000 0000 uuuu uuuu pcon 8eh ---1 --0x ---u --uq (1,5) ---u --uu osccon 8fh -110 x000 -110 x000 -uuu uuuu osctune 90h ---0 0000 ---u uuuu ---u uuuu ansel0 91h 1111 1111 1111 1111 uuuu uuuu pr2 92h 1111 1111 1111 1111 1111 1111 legend: u = unchanged, x = unknown, ? = unimplemented bit, reads as ? 0 ?, q = value depends on condition. note 1: if v dd goes too low, power-on reset will be activated and registers will be affected differently. 2: one or more bits in intcon and/or pir1 will be affected (to cause wake-up). 3: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 4: see table 15-5 for reset value for specific condition. 5: if reset was due to brown-out, then bit 0 = 0 . all other resets will cause bit 0 = u . 6: analog channels read 0 but data latches are unknown. 7: analog channels read 0 but data latches are unchanged.
? 2004 microchip technology inc. preliminary ds41249a-page 111 PIC16F785 ansel1 93h ---- 1111 ---- 1111 ---- uuuu wpua 95h --11 1111 --11 1111 --uu uuuu ioca 96h --00 0000 --00 0000 --uu uuuu refcon 98h --00 000- --00 000- --uu uuu- vrcon 99h 000- 0000 000- 0000 uuu- uuuu eedat 9ah 0000 0000 0000 0000 uuuu uuuu eeadr 9bh 0000 0000 0000 0000 uuuu uuuu eecon1 9ch ---- x000 ---- q000 ---- uuuu eecon2 9dh ---- ---- ---- ---- ---- ---- adresl 9eh xxxx xxxx uuuu uuuu uuuu uuuu adcon1 9fh -000 ---- -000 ---- -uuu ---- pwmcon1 110h 0000 0000 0000 0000 uuuu uuuu pwmcon0 111h 0000 0000 0000 0000 uuuu uuuu pwmclk 112h 0000 0000 0000 0000 uuuu uuuu pwmph1 113h 0000 0000 0000 0000 uuuu uuuu pwmph2 114h 0000 0000 0000 0000 uuuu uuuu cm1con0 119h 0000 0000 0000 0000 uuuu uuuu cm2con0 11ah 0000 0000 0000 0000 uuuu uuuu cm2con1 11bh 00-- --10 00-- --10 uu-- --uu opa1con 11ch 0--- ---- 0--- ---- u--- ---- opa2con 11dh 0--- ---- 0--- ---- u--- ---- table 15-4: initialization condition for registers (continued) register address power-on reset mclr reset wdt reset (continued) brown-out reset (1) wake-up from sleep through interrupt wake-up from sleep through wdt time out legend: u = unchanged, x = unknown, ? = unimplemented bit, reads as ? 0 ?, q = value depends on condition. note 1: if v dd goes too low, power-on reset will be activated and registers will be affected differently. 2: one or more bits in intcon and/or pir1 will be affected (to cause wake-up). 3: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 4: see table 15-5 for reset value for specific condition. 5: if reset was due to brown-out, then bit 0 = 0 . all other resets will cause bit 0 = u . 6: analog channels read 0 but data latches are unknown. 7: analog channels read 0 but data latches are unchanged.
PIC16F785 ds41249a-page 112 preliminary ? 2004 microchip technology inc. table 15-5: initialization condition for special registers condition program counter status register pcon register power-on reset 000h 0001 1xxx ---1 --0x mclr reset during normal operation 000h 000u uuuu ---u --uu mclr reset during sleep 000h 0001 0uuu ---u --uu wdt reset 000h 0000 uuuu ---u --uu wdt wake-up pc + 1 uuu0 0uuu ---u --uu brown-out reset 000h 0001 1uuu ---1 --10 interrupt wake-up from sleep pc + 1 (1) uuu1 0uuu ---u --uu legend: u = unchanged, x = unknown, ? = unimplemented bit, reads as ? 0 ?. note 1: when the wake-up is due to an interrupt and global enable bit gie is set, the pc is loaded with the interrupt vector (0004h) after execution of pc+1.
? 2004 microchip technology inc. preliminary ds41249a-page 113 PIC16F785 15.4 interrupts the PIC16F785 has 11 sources of interrupt: external interrupt ra2/int tmr0 overflow interrupt porta change interrupt 2 comparator interrupts a/d interrupt timer 1 overflow interrupt timer 2 match interrupt eeprom data write interrupt fail-safe clock monitor interrupt ccp interrupt the interrupt control register (intcon) and peripheral interrupt register (pir1) record individual interrupt requests in flag bits. the intcon register also has individual and global interrupt enable bits. a global interrupt enable bit, gie (intcon<7>) enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. individual interrupts can be disabled through their corresponding enable bits in intcon register and pie1 register. gie is cleared on reset. the return from interrupt instruction, retfie , exits interrupt routine, as well as sets the gie bit, which re- enables unmasked interrupts. the following interrupt flags are contained in the intcon register: int pin interrupt porta change interrupt tmr0 overflow interrupt the peripheral interrupt flags are contained in the special register pir1. the corresponding interrupt enable bit is contained in special register pie1. the following interrupt flags are contained in the pir1 register: eeprom data write interrupt a/d interrupt 2 comparator interrupts timer1 overflow interrupt timer 2 match interrupt fail-safe clock monitor interrupt ccp interrupt when an interrupt is serviced: the gie is cleared to disable any further interrupt the return address is pushed onto the stack the pc is loaded with 0004h for external interrupt events, such as the int pin or porta change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends upon when the interrupt event occurs (see figure 15-8). the latency is the same for one or two- cycle instructions. once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid multiple interrupt requests. for additional information on timer1, timer2, comparators, a/d, data eeprom or ccp modules, refer to the respective peripheral section. note 1: individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the gie bit. 2: when an instruction that clears the gie bit is executed, any interrupts that were pending for execution in the next cycle are ignored. the interrupts, which were ignored, are still pending to be serviced when the gie bit is set again.
PIC16F785 ds41249a-page 114 preliminary ? 2004 microchip technology inc. 15.4.1 ra2/an2/t0cki/int/c1out interrupt external interrupt on ra2/an2/t0cki/int/c1out pin is edge-triggered; either rising, if intedg bit (option<6>) is set, or falling, if intedg bit is clear. when a valid edge appears on the ra2/an2/t0cki/ int/c1out pin, the intf bit (intcon<1>) is set. this interrupt can be disabled by clearing the inte control bit (intcon<4>). the intf bit must be cleared in soft- ware in the interrupt service routine before re- enabling this interrupt. the ra2/an2/t0cki/int/ c1out interrupt can wake-up the processor from sleep if the inte bit was set prior to going into sleep. the status of the gie bit decides whether or not the processor branches to the interrupt vector following wake-up (0004h). see section 15.7 ?power-down mode (sleep)? for details on sleep and figure 15-10 for timing of wake-up from sleep through ra2/an2/ t0cki/int/c1out interrupt. 15.4.2 tmr0 interrupt an overflow (ffh 00h) in the tmr0 register will set the t0if (intcon<2>) bit. the interrupt can be enabled/disabled by setting/clearing t0ie (intcon<5>) bit. see section 5.0 ?timer0 module? for operation of the timer0 module. 15.4.3 porta interrupt an input change on porta change sets the raif (intcon<0>) bit. the interrupt can be enabled/ disabled by setting/clearing the raie (intcon<3>) bit. plus, individual pins can be configured through the ioca register. figure 15-7: interrupt logic note: the ansel0 (91h), and ansel1 (93h) registers must be initialized to configure an analog channel as a digital input. pins configured as analog inputs will read ? 0 ?. note: if a change on the i/o pin should occur when the read operation is being executed (start of the q2 cycle), then the raif interrupt flag may not get set. tmr1if tmr1ie c1if c1ie t0if t0ie intf inte raif raie gie peie wake-up (if in sleep mode) interrupt to cpu eeie eeif adif adie ioc-ra0 ioca0 ioc-ra1 ioca1 ioc-ra2 ioca2 ioc-ra3 ioca3 ioc-ra4 ioca4 ioc-ra5 ioca5 tmr2if tmr2ie ccp1if ccp1ie osfif osfie c2if c2ie
? 2004 microchip technology inc. preliminary ds41249a-page 115 PIC16F785 figure 15-8: int pin interrupt timing table 15-6: summary of interrupt registers addressnamebit 7bit 6bit 5bit 4bit 3bit 2 bit 1bit 0 value on: por, bor value on all other resets 0bh, 8bh intcon gie peie t0ie inte raie t0if intf raif 0000 0000 0000 0000 0ch pir1 eeif adif ccp1if c2if c1if osfif tmr2if tmr1if 0000 0000 0000 0000 8ch pie1 eeie adie ccp1ie c2ie c1ie osfie tmr2ie tmr1ie 0000 0000 0000 0000 legend: x = unknown, u = unchanged, ? = unimplemented read as ? 0 ?, q = value depends upon condition. shaded cells are not used by the interrupt module. q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 clkout int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed interrupt latency pc pc+1 pc+1 0004h 0005h inst (0004h) inst (0005h) dummy cycle inst (pc) inst (pc+1) inst (pc-1) inst (0004h) dummy cycle inst (pc) ? note 1: intf flag is sampled here (every q1). 2: asynchronous interrupt latency = 3 ? 4 t cy . synchronous latency = 3 t cy , where t cy = instruction cycle time. latency is the same whether inst (pc) is a single cycle or a 2-cycle instruction. 3: clkout is available only in intosc and rc oscillator modes. 4: for minimum width of int pulse, refer to ac specifications in section 18.0 ?electrical specifications? . 5: intf is enabled to be set any time during the q4 ? q1 cycles. (1) (2) (3) (4) (5) (1)
PIC16F785 ds41249a-page 116 preliminary ? 2004 microchip technology inc. 15.5 context saving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users may wish to save key registers during an interrupt (e.g., w and status registers). this must be implemented in software. since the last 16 bytes of all banks are common in the PIC16F785 (see figure 2-2), temporary holding registers w_temp and status_temp should be placed in here. these 16 locations do not require banking therefore, making it easier to save and restore context. the same code shown in example 15-1 can be used to: store the w register store the status register execute the isr code restore the status (and bank select bit register) restore the w register example 15-1: saving status and w registers in ram note: the PIC16F785 normally does not require saving the pclath. however, if com- puted goto ?s are used in the isr and the main code, the pclath must be saved and restored in the isr. movwf w_temp ;copy w to temp register swapf status,w ;swap status to be saved into w (swap does not affect status) clrf status ;bank 0, regardless of current bank, clears irp,rp1,rp0 movwf status_temp ;save status to bank zero status_temp register : :(isr) ;insert user code here : swapf status_temp,w ;swap status_temp register into w ;(sets bank to original state) movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w
? 2004 microchip technology inc. preliminary ds41249a-page 117 PIC16F785 15.6 watchdog timer (wdt) for PIC16F785, the wdt has been modified from previous pic16f devices. the new wdt is code and functionally compatible with previous pic16f wdt modules and adds a 16-bit prescaler to the wdt. this allows the user to scale the value for the wdt and tmr0 at the same time. in addition, the wdt timeout value can be extended to 268 seconds. wdt is cleared under certain conditions described in table 15-7. 15.6.1 wdt oscillator the wdt derives its time base from the 31 khz lfintosc. the lts bit does not reflect that the lfintosc is enabled (oscon<1>). the value of wdtcon is ? ---0 1000 ? on all resets. this gives a nominal time base of 16 ms, which is com- patible with the time base generated with previous pic16f microcontroller versions. a new prescaler has been added to the path between the intrc and the multiplexers used to select the path for the wdt. this prescaler is 16 bits and can be programmed to divide the intrc by 128 to 65536, giving the time base used for the wdt a nominal range of 1 ms to 268s. 15.6.2 wdt control the wdte bit is located in the configuration word. when set, the wdt runs continuously. when the wdte bit in the configuration word register is set, the swdten bit (wdtcon<0>) has no effect. if wdte is clear, then the swdten bit can be used to enable and disable the wdt. setting the bit will enable it and clearing the bit will disable it. the psa and ps<2:0> bits (option_reg) have the same function as in previous versions of the pic16f family of microcontrollers. see section 5.0 ?timer0 module? for more information. figure 15-9: watchdog timer block diagram note: when the oscillator start-up timer (ost) is invoked, the wdt is held in reset, because the wdt ripple counter is used by the ost to perform the oscillator delay count. when the ost count has expired, the wdt will begin counting (if enabled). table 15-7: wdt status conditions wdt wdte = 0 cleared clrwdt command osc fail detected exit sleep + system clock = t1osc, extrc, intrc, extclk exit sleep + system clock = xt, hs, lp cleared until the end of ost 31 khz psa 16-bit wdt prescaler from tmr0 clock source prescaler (1) 8 ps<2:0> psa wdt timeout to tmr0 wdtps<3:0> wdte from configuration word 1 1 0 0 swdten from wdtcon lfintosc clock note 1 : this is the shared timer0/wdt prescaler. see section 5.4 ?prescaler? for more information.
PIC16F785 ds41249a-page 118 preliminary ? 2004 microchip technology inc. register 15-2: wdtcon ? watchdog timer control register (address: 18h) table 15-8: summary of watchdog timer registers u-0 u-0 u-0 r/w-0 r/w-1 r/w-0 r/w-0 r/w-0 ? ? ? wdtps3 wdtps2 wdtps1 wdtps0 swdten bit 7 bit 0 bit 7-5 unimplemented: read as ? 0 ? bit 4-1 wdtps<3:0>: watchdog timer period select bits bit value = prescale rate 0000 = 1:32 0001 = 1:64 0010 = 1:128 0011 = 1:256 0100 = 1:512 (reset value) 0101 = 1:1024 0110 = 1:2048 0111 = 1:4096 1000 = 1:8192 1001 = 1:16384 1010 = 1:32768 1011 = 1:65536 1100 = reserved 1101 = reserved 1110 = reserved 1111 = reserved bit 0 swdten: software enable or disable the watchdog timer bit (1) 1 = wdt is turned on 0 = wdt is turned off (reset value) note 1: if wdte configuration bit = 1 , then wdt is always enabled, irrespective of this control bit. if wdte configuration bit = 0 , then it is possible to turn wdt on/off with this control bit. legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? - n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on: por,bor value on all other resets 18h wdtcon ? ? ? wdtps3 wdtps2 wstps1 wdtps0 swdten ---0 1000 ---0 1000 81h/ 181h option_reg rapu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 2007h (1) config cpd cp mclre pwrte wdte fosc2 fosc1 fosc0 uuuu uuuu uuuu uuuu legend: shaded cells are not used by the watchdog timer. note 1: see register 15-1 for operation of all configuration word bits.
? 2004 microchip technology inc. preliminary ds41249a-page 119 PIC16F785 15.7 power-down mode (sleep) the power-down mode is entered by executing a sleep instruction. if the watchdog timer is enabled: wdt will be cleared but keeps running. pd bit in the status register is cleared. to bit is set. oscillator driver is turned off. i/o ports maintain the status they had before sleep was executed (driving high, low or high- impedance). for lowest current consumption in this mode, all i/o pins should be either at v dd or v ss , with no external circuitry drawing current from the i/o pin, and all unused peripheral modules should be disabled. digital i/o pins that are high-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. the t0cki input should also be at v dd or v ss for lowest current consumption. the contribution from on-chip pull-ups on porta should be considered. the mclr pin must be at a logic high level. 15.7.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin 2. watchdog timer wake-up (if wdt was enabled) 3. interrupt from ra2/an2/t0cki/int/c1out pin, porta change or a peripheral interrupt. the first event will cause a device reset. the two latter events are considered a continuation of program exe- cution. the to and pd bits in the status register can be used to determine the cause of device reset. the pd bit, which is set on power-up, is cleared when sleep is invoked. to bit is cleared if wdt wake-up occurred. the following peripheral interrupts can wake the device from sleep: 1. tmr1 interrupt. timer1 must be operating as an asynchronous counter. 2. ccp capture mode interrupt 3. a/d conversion (when a/d clock source is rc) 4. eeprom write operation completion 5. comparator output changes state 6. interrupt-on-change 7. external interrupt from int pin other peripherals cannot generate interrupts since, during sleep, no on-chip clocks are present. when the sleep instruction is being executed, the next instruction (pc + 1) is pre-fetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit (and pie bit where applicable) must be set (enabled). wake-up is regardless of the state of the gie bit. if the gie bit is clear (disabled), the device continues execution at the instruction after the sleep instruction. if the gie bit is set (enabled), the device executes the instruction after the sleep instruction, then branches to the interrupt address (0004h). in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. the wdt is cleared when the device wakes up from sleep, regardless of the source of wake-up. 15.7.2 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: if the interrupt occurs before the execution of a sleep instruction, the sleep instruction will complete as a nop . therefore, the wdt and wdt prescaler and postscaler (if enabled) will not be cleared, the to bit will not be set and the pd bit will not be cleared. if the interrupt occurs during or after the execu- tion of a sleep instruction, the device will immediately wake-up from sleep. the sleep instruction will be completely executed before the wake-up. therefore, the wdt and wdt prescaler and postscaler (if enabled) will be cleared, the to bit will be set, and the pd bit will be cleared. even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . to ensure that the wdt is cleared, a clrwdt instruction should be executed before a sleep instruction. note: it should be noted that a reset generated by a wdt time out does not drive mclr pin low. note: if the global interrupts are disabled (gie is cleared), but any interrupt source has both its interrupt enable bit and the correspond- ing interrupt flag bits set, the device will immediately wake-up from sleep. the sleep instruction is completely executed.
PIC16F785 ds41249a-page 120 preliminary ? 2004 microchip technology inc. figure 15-10: wake-up from sleep through interrupt (1) q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout (4) int pin intf flag (intcon<1>) gie bit (intcon<7>) instruction flow pc instruction fetched instruction executed pc pc+1 pc+2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (3) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost (2) pc+2 note 1: xt, hs or lp oscillator mode assumed. 2: t ost = 1024t osc (drawing not to scale). this delay does not apply to ec, rc and intosc oscillator modes. 3: gie = ? 1 ? assumed. in this case after wake-up, the processor jumps to 0004h. if gie = ? 0 ?, execution will continue in-line. 4: clkout is not available in xt, hs, lp or ec oscillator modes, but shown here for timing reference.
? 2004 microchip technology inc. preliminary ds41249a-page 121 PIC16F785 15.8 code protection if the code protection bit(s) have not been programmed, the on-chip program memory can be read out using icsp for verification purposes. 15.9 id locations four memory locations (2000h ? 2003h) are desig- nated as id locations where the user can store check- sum or other code identification numbers. these locations are not accessible during normal execution, but are readable and writable during program/verify. only the least significant 7 bits of the id locations are used. 15.10 in-circuit serial programming the PIC16F785 microcontrollers can be serially programmed while in the end application circuit. this is simply done with five lines: clock data power ground programming voltage this allows customers to manufacture boards with unprogrammed devices and then program the micro- controller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. the device is placed into a program/verify mode by holding the ra0 and ra1 pins low, while raising the mclr (v pp ) pin from v il to v ihh . see the PIC16F785 memory programming specification (ds41237) for more information. ra0 becomes the programming data and ra1 becomes the programming clock. both ra0 and ra1 are schmitt trigger inputs in this mode. after reset, to place the device into program/verify mode, the program counter (pc) is at location 00h. a 6-bit command is then supplied to the device. depending on the command, 14 bits of program data are then supplied to or from the device, depending on whether the command was a load or a read. for complete details of serial programming, please refer to the PIC16F785 memory programming specification (ds41237). a typical in-circuit serial programming connection is shown in figure 15-11. figure 15-11: typical in-circuit serial programming connection note: the entire data eeprom and flash program memory will be erased when the code protection is turned off by performing a bulk erase. see the PIC16F785 memory programming specification (ds41237) for more information. external connector signals to n o r m a l connections to n o rm a l connections v dd v ss mclr /v pp /ra3 ra1 ra0 +5v 0v v pp clk data i/o * * * * * isolation devices (as required) PIC16F785
PIC16F785 ds41249a-page 122 preliminary ? 2004 microchip technology inc. 15.11 in-circuit debugger in-circuit debugging requires clock, data and mclr pins. a special 28-pin PIC16F785 icd device is used with mplab ? icd 2 to provide separate clock, data and mclr pins so that no pins are lost for these func- tions leaving all 18 of the PIC16F785 i/o pins available to the user during debug operation. this special icd device is mounted on the top of a header and its signals are routed to the mplab icd 2 connector. on the bottom of the header is a 20-pin socket that plugs into the user?s target via the 20-pin stand-off connector. when the icd pin on the PIC16F785 icd device is held low, the in-circuit debugger functionality is enabled. this function allows simple debugging functions when used with mplab icd 2. when the microcontroller has this feature enabled, some of the resources are not available for general use. table 15-9 shows which fea- tures are consumed by the background debugger: table 15-9: debugger resources for more information, see mplab ? icd 2 in-circuit debugger user?s guide (ds51292), available on microchip?s web site (www.microchip.com). figure 15-12: 28-pin icd pinout resource description i/o pins icdclk, icddata stack 1 level program memory address 0h must be nop 700h ? 7ffh 28-pin pdip PIC16F785 -icd in-circuit debug device shntreg icdmclr /v pp v dd ra5 ra4 ra3 icdclk icddata vss ra0 rc6 rb4 ra1 ra2 rc5 rc4 rc3 rc0 rc1 rc2 1 2 3 4 5 6 7 8 9 10 28 27 26 25 24 23 22 21 20 19 nc nc rc7 rb7 icd rb5 rb6 nc 11 12 13 14 18 17 16 15
? 2004 microchip technology inc. preliminary ds41249a-page 123 PIC16F785 16.0 instruction set summary the PIC16F785 instruction set is highly orthogonal and is comprised of three basic categories: byte-oriented operations bit-oriented operations literal and control operations each pic16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the format for each of the categories is presented in figure 16-1, while the various opcode fields are summarized in table 16-1. table 16-2 lists the instructions recognized by the mpasm tm assembler. a complete description of each instruction is also available in the picmicro ? mid- range reference manual (ds33023). for byte-oriented instructions, ? f ? represents a file register designator and ? d ? represents a destination designator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if ? d ? is zero, the result is placed in the w register. if ? d ? is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, ? b ? represents a bit field designator, which selects the bit affected by the operation, while ? f ? represents the address of the file in which the bit is located. for literal and control operations, ? k ? represents an 8-bit or 11-bit constant, or literal value. one instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 mhz, this gives a normal instruction execution time of 1 s. all instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. when this occurs, the execution takes two instruction cycles, with the second cycle executed as a nop . all instruction examples use the format ?0xhh? to represent a hexadecimal number, where ?h? signifies a hexadecimal digit. 16.1 read-modify-write operations any instruction that specifies a file register as part of the instruction performs a read-modify-write (r-m-w) operation. the register is read, the data is modified, and the result is stored according to either the instruc- tion, or the destination designator ?d?. a read operation is always performed, even if the instruction is a write command. for example, a clrf porta instruction will read porta, clear all the data bits, then write the result back to porta. this example would have the unintended result of clearing the condition that set the raif flag. table 16-1: opcode field descriptions figure 16-1: general format for instructions note: to maintain upward compatibility with future products, do not use the option and tris instructions. field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don't care location (= 0 or 1 ). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 : store result in w, d = 1 : store result in file register f. default is d = 1. pc program counter to time-out bit pd power-down bit byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only
PIC16F785 ds41249a-page 124 preliminary ? 2004 microchip technology inc. table 16-2: PIC16F785 instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f - f, d f, d f, d f, d f, d f, d f, d f - f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1 (2) 1 1 (2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z z z z c c c,dc,z z 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1,2 1,2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k - k k k - k - - k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c,dc,z z to ,pd z to ,pd c,dc,z z note 1: when an i/o register is modified as a function of itself (e.g., movf porta, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tm r0 register (and, where applicable, d = 1 ), the prescaler will be cleared if assigned to the timer0 module. 3: if program counter (pc) is modified, or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . note: additional information on the mid-range instruction set is available in the picmicro ? mid-range mcu family reference manual (ds33023).
? 2004 microchip technology inc. preliminary ds41249a-page 125 PIC16F785 16.2 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 k 255 operation: (w) + k (w) status affected: c, dc, z description: the contents of the w register are added to the eight-bit literal ?k? and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 127 d [0,1] operation: (w) + (f) (destination) status affected: c, dc, z description: add the contents of the w register with register ?f?. if ?d? is 0 , the result is stored in the w register. if ?d? is 1, the result is stored back in register ?f?. andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w) .and. (k) (w) status affected: z description: the contents of w register are and?ed with the eight-bit literal ?k?. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 127 d [0,1] operation: (w) .and. (f) (destination) status affected: z description: and the w register with register ?f?. if ?d? is 0 , the result is stored in the w register. if ?d? is 1 , the result is stored back in register ?f?. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 127 0 b 7 operation: 0 (f) status affected: none description: bit ?b? in register ?f? is cleared. bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 127 0 b 7 operation: 1 (f) status affected: none description: bit ?b? in register ?f? is set. btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 127 0 b 7 operation: skip if (f) = 0 status affected: none description: if bit ?b? in register ?f'? is ? 1 ?, the next instruction is executed. if bit ?b?, in register ?f?, is ? 0 ?, the next instruction is discarded, and a nop is executed instead, making this a 2-cycle instruction. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 127 0 b < 7 operation: skip if (f) = 1 status affected: none description: if bit ?b? in register ?f? is ? 0 ?, the next instruction is executed. if bit ?b? is ? 1 ?, then the next instruc- tion is discarded and a nop is executed instead, making this a 2-cycle instruction.
PIC16F785 ds41249a-page 126 preliminary ? 2004 microchip technology inc. call call subroutine syntax: [ label ] call k operands: 0 k 2047 operation: (pc)+ 1 tos, k pc<10:0>, (pclath<4:3>) pc<12:11> status affected: none description: call subroutine. first, return address (pc+1) is pushed onto the stack. the eleven-bit immedi- ate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 f 127 operation: 00h (f) 1 z status affected: z description: the contents of register ?f? are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h (w) 1 z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h wdt 0 wdt prescaler, 1 to 1 pd status affected: to , pd description: clrwdt instruction resets the watchdog timer. it also resets the prescaler of the wdt. status bits to and pd are set. comf complement f syntax: [ label ] comf f,d operands: 0 f 127 d [0,1] operation: (f ) (destination) status affected: z description: the contents of register ?f? are complemented. if ?d? is 0 , the result is stored in w. if ?d? is 1 , the result is stored back in register ?f?. decf decrement f syntax: [ label ] decf f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (destination) status affected: z description: decrement register ?f?. if ?d? is 0 , the result is stored in the w register. if ?d? is 1 , the result is stored back in register ?f?. decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 127 d [0,1] operation: (f) - 1 (destination); skip if result = 0 status affected: none description: the contents of register ?f? are decremented. if ?d? is 0 , the result is placed in the w register. if ?d? is 1 , the result is placed back in register ?f?. if the result is 1 , the next instruc- tion is executed. if the result is 0 , then a nop is executed instead, making it a 2-cycle instruction.
? 2004 microchip technology inc. preliminary ds41249a-page 127 PIC16F785 goto unconditional branch syntax: [ label ] goto k operands: 0 k 2047 operation: k pc<10:0> pclath<4:3> pc<12:11> status affected: none description: goto is an unconditional branch. the eleven-bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two- cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (destination) status affected: z description: the contents of register ?f? are incremented. if ?d? is 0 , the result is placed in the w register. if ?d? is 1 , the result is placed back in register ?f?. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 127 d [0,1] operation: (f) + 1 (destination), skip if result = 0 status affected: none description: the contents of register ?f? are incremented. if ?d? is 0 , the result is placed in the w register. if ?d? is 1 , the result is placed back in register ?f?. if the result is 1 , the next instruc- tion is executed. if the result is 0 , a nop is executed instead, making it a 2-cycle instruction. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. k (w) status affected: z description: the contents of the w register are or?ed with the eight-bit literal ?k?. the result is placed in the w register. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 127 d [0,1] operation: (w) .or. (f) (destination) status affected: z description: inclusive or the w register with register ?f?. if ?d? is 0 , the result is placed in the w register. if ?d? is 1 , the result is placed back in register ?f?. movf move f syntax: [ label ] movf f,d operands: 0 f 127 d [0,1] operation: (f) (dest) status affected: z encoding: 00 1000 dfff ffff description: the contents of register ?f? is moved to a destination dependent upon the status of d. if ?d? = 0 , destination is w register. if ?d? = 1 , the destination is file register ?f? itself. ?d? = 1 is useful to test a file register since status flag z is affected. words: 1 cycles: 1 example movf fsr, 0 after instruction w = value in fsr register z= 1
PIC16F785 ds41249a-page 128 preliminary ? 2004 microchip technology inc. movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k (w) status affected: none encoding: 11 00xx kkkk kkkk description: the eight bit literal ?k? is loaded into w register. the don?t cares will assemble as 0 ?s . words: 1 cycles: 1 example movlw 0x5a after instruction w = 0x5a movwf move w to f syntax: [ label ] movwf f operands: 0 f 127 operation: (w) (f) status affected: none encoding: 00 0000 1fff ffff description: move data from w register to register ?f?. words: 1 cycles: 1 example movwf option before instruction option = 0xff w = 0x4f after instruction option = 0x4f w = 0x4f nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 00 0000 0xx0 0000 description: no operation. words: 1 cycles: 1 example nop retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos pc, 1 gie status affected: none encoding: 00 0000 0000 1001 description: return from interrupt. stack is poped and top of stack (tos) is loaded in the pc. interrupts are enabled by setting global interrupt enable bit, gie (intcon<7>). this is a two-cycle instruction. words: 1 cycles: 2 example retfie after interrupt pc = tos gie = 1
? 2004 microchip technology inc. preliminary ds41249a-page 129 PIC16F785 retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k (w); tos pc status affected: none encoding: 11 01xx kkkk kkkk description: the w register is loaded with the eight bit literal ?k?. the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. words: 1 cycles: 2 example table call table;w contains table ;offset value ;w now has table value addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; retlw kn ; end of table before instruction w = 0x07 after instruction w = value of k8 return return from subroutine syntax: [ label ] return operands: none operation: tos pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two-cycle instruction. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c encoding: 00 1101 dfff ffff description: the contents of register ?f? are rotated one bit to the left through the carry flag. if ?d? is 0 , the result is placed in the w register. if ?d? is 1 , the result is stored back in register ?f?. words: 1 cycles: 1 example rlf reg1,0 before instruction reg1 = 1110 0110 c=0 after instruction reg1 = 1110 0110 w = 1100 1100 c=1 register f c
PIC16F785 ds41249a-page 130 preliminary ? 2004 microchip technology inc. rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 127 d [0,1] operation: see description below status affected: c encoding: 00 1100 dfff ffff description: the contents of register ?f? are rotated one bit to the right through the carry flag. if ?d? is 0 the result is placed in the w register. if ?d? is 1 the result is placed back in register ?f?. words: 1 cycles: 1 example rrf reg1, 0 before instruction reg1 = 1110 0110 c =0 after instruction reg1 = 1110 0110 w = 0111 0011 c =0 sleep syntax: [ labe l] sleep operands: none operation: 00h wdt, 0 wdt prescaler, 1 to , 0 pd status affected: to , pd encoding: 00 0000 0110 0011 description: the power-down status bit, pd is cleared. time out status bit, to is set. watchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscilla- tor stopped. words: 1 cycles: 1 example: sleep register f c sublw subtract w from literal syntax: [ label ]sublw k operands: 0 k 255 operation: k - (w) ( w) status affected: c, dc, z encoding: 11 110x kkkk kkkk description: the w register is subtracted (2?s complement method) from the eight bit literal ?k?. the result is placed in the w register. words: 1 cycles: 1 example 1: sublw 0x02 before instruction w=1 c=? after instruction w= 1 c = 1; result is positive example 2: before instruction w= 2 c=? after instruction w= 0 c = 1; result is zero example 3: before instruction w= 3 c= ? after instruction w= 0xff c = 0; result is negative
? 2004 microchip technology inc. preliminary ds41249a-page 131 PIC16F785 subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 f 127 d [0,1] operation: (f) - (w) ( dest) status affected: c, dc, z encoding: 00 0010 dfff ffff description: subtract (2?s complement method) w register from register ?f?. if ?d? is 0 the result is stored in the w register. if ?d? is 1 the result is stored back in register ?f?. words: 1 cycles: 1 example 1: subwf reg1, 1 before instruction reg1 = 3 w=2 c=? after instruction reg1 = 1 w=2 c = 1; result is positive z=0 dc = 1 example 2: before instruction reg1 = 2 w=2 c=? after instruction reg1 = 0 w=2 c = 1; result is zero z = dc = 1 example 3: before instruction reg1 = 1 w=2 c=? after instruction reg1 = 0xff w=2 c = 0; result is negative z = dc = 0 swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 127 d [0,1] operation: (f<3:0>) (dest<7:4>), (f<7:4>) (dest<3:0>) status affected: none encoding: 00 1110 dfff ffff description: the upper and lower nibbles of register ?f? are exchanged. if ?d? is 0 the result is placed in w regis- ter. if ?d? is 1 the result is placed in register ?f?. words: 1 cycles: 1 example swapf reg1, 0 before instruction reg1 = 0xa5 after instruction reg1 = 0xa5 w = 0x5a tris load tris register syntax: [ label ] tris f operands: 5 f 6 operation: (w) tris register f; status affected: none encoding: 00 0000 0110 0fff description: the instruction is supported for code compatibility with the pic16c5x products. since tris registers are readable and writ- able, the user can directly address them. words: 1 cycles: 1 example to maintain upward compatibil- ity with future picmicro ? products, do not use this instruction.
PIC16F785 ds41249a-page 132 preliminary ? 2004 microchip technology inc. xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 k 255 operation: (w) .xor. k ( w) status affected: z encoding: 11 1010 kkkk kkkk description: the contents of the w register are xor?ed with the eight bit literal ?k?. the result is placed in the w register. words: 1 cycles: 1 example: xorlw 0xaf before instruction w=0xb5 after instruction w = 0x1a xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 127 d [0,1] operation: (w) .xor. (f) ( dest) status affected: z encoding: 00 0110 dfff ffff description: exclusive or the contents of the w register with register ?f?. if ?d? is 0 the result is stored in the w reg- ister. if ?d? is 1 the result is stored back in register ?f?. words: 1 cycles: 1 example xorwf reg1, 1 before instruction reg1 = 0xaf w=0xb5 after instruction reg1 = 0x1a w=0xb5
? 2004 microchip technology inc. preliminary ds41249a-page 133 PIC16F785 17.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: integrated development environment - mplab ? ide software assemblers/compilers/linkers - mpasm tm assembler - mplab c17 and mplab c18 c compilers -mplink tm object linker/ mplib tm object librarian - mplab c30 c compiler - mplab asm30 assembler/linker/library simulators - mplab sim software simulator - mplab dspic30 software simulator emulators - mplab ice 2000 in-circuit emulator - mplab ice 4000 in-circuit emulator in-circuit debugger - mplab icd 2 device programmers -pro mate ? ii universal device programmer - picstart ? plus development programmer - mplab pm3 device programmer low-cost demonstration boards - picdem tm 1 demonstration board - picdem.net tm demonstration board - picdem 2 plus demonstration board - picdem 3 demonstration board - picdem 4 demonstration board - picdem 17 demonstration board - picdem 18r demonstration board - picdem lin demonstration board - picdem usb demonstration board evaluation kits -k ee l oq ? security ics - picdem msc -microid ? rfid -can - powersmart ? battery management -analog 17.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. the mplab ide is a windows ? based application that contains: an interface to debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) a full-featured editor with color coded context a multiple project manager customizable data windows with direct edit of contents high-level source code debugging mouse over variable inspection extensive on-line help the mplab ide allows you to: edit your source files (either assembly or c) one touch assemble (or compile) and download to picmicro emulator and simulator tools (automatically updates all project information) debug using: - source files (assembly or c) - mixed assembly and c - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increasing flexibility and power. 17.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all picmicro mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol ref- erence, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: integration into mplab ide projects user defined macros to streamline assembly code conditional assembly for multi-purpose source files directives that allow complete control over the assembly process
PIC16F785 ds41249a-page 134 preliminary ? 2004 microchip technology inc. 17.3 mplab c17 and mplab c18 c compilers the mplab c17 and mplab c18 code development systems are complete ansi c compilers for microchip?s pic17cxxx and pic18cxxx family of microcontrollers. these compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 17.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c17 and mplab c18 c compilers. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: efficient linking of single libraries instead of many smaller files enhanced code maintainability by grouping related modules together flexible creation of libraries with easy module listing, replacement, deletion and extraction 17.5 mplab c30 c compiler the mplab c30 c compiler is a full-featured, ansi compliant, optimizing compiler that translates standard ansi c programs into dspic30f assembly language source. the compiler also supports many command line options and language extensions to take full advantage of the dspic30f device hardware capabili- ties and afford fine control of the compiler code generator. mplab c30 is distributed with a complete ansi c standard library. all library functions have been vali- dated and conform to the ansi c library standard. the library includes functions for string manipulation, dynamic memory allocation, data conversion, time- keeping and math functions (trigonometric, exponential and hyperbolic). the compiler provides symbolic information for high-level source debugging with the mplab ide. 17.6 mplab asm30 assembler, linker and librarian mplab asm30 assembler produces relocatable machine code from symbolic assembly language for dspic30f devices. mplab c30 compiler uses the assembler to produce it?s object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: support for the entire dspic30f instruction set support for fixed-point and floating-point data command line interface rich directive set flexible macro language mplab ide compatibility 17.7 mplab sim software simulator the mplab sim software simulator allows code devel- opment in a pc hosted environment by simulating the picmicro series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any pin. the execu- tion can be performed in single-step, execute until break or trace mode. the mplab sim simulator fully supports symbolic debugging using the mplab c17 and mplab c18 c compilers, as well as the mpasm assembler. the software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent, economical software development tool. 17.8 mplab sim30 software simulator the mplab sim30 software simulator allows code development in a pc hosted environment by simulating the dspic30f series microcontrollers on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user defined key press, to any of the pins. the mplab sim30 simulator fully supports symbolic debugging using the mplab c30 c compiler and mplab asm30 assembler. the simulator runs in either a command line mode for automated tasks, or from mplab ide. this high-speed simulator is designed to debug, analyze and optimize time intensive dsp routines.
? 2004 microchip technology inc. preliminary ds41249a-page 135 PIC16F785 17.9 mplab ice 2000 high-performance universal in-circuit emulator the mplab ice 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator sys- tem with enhanced trace, trigger and data monitoring features. interchangeable processor modules allow the system to be easily reconfigured for emulation of differ- ent processors. the universal architecture of the mplab ice in-circuit emulator allows expansion to support new picmicro microcontrollers. the mplab ice 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft ? windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 17.10 mplab ice 4000 high-performance universal in-circuit emulator the mplab ice 4000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for high- end picmicro microcontrollers. software control of the mplab ice in-circuit emulator is provided by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab icd 4000 is a premium emulator system, providing the features of mplab ice 2000, but with increased emulation memory and high-speed perfor- mance for dspic30f and pic18xxxx devices. its advanced emulator features include complex triggering and timing, up to 2 mb of emulation memory and the ability to view variables in real-time. the mplab ice 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 17.11 mplab icd 2 in-circuit debugger microchip?s in-circuit debugger, mplab icd 2, is a powerful, low-cost, run-time development tool, connecting to the host pc via an rs-232 or high-speed usb interface. this tool is based on the flash picmicro mcus and can be used to develop for these and other picmicro microcontrollers. the mplab icd 2 utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip?s in-circuit serial programming tm (icsp tm ) protocol, offers cost effective in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by setting breakpoints, single-stepping and watching variables, cpu status and peripheral registers. running at full speed enables testing hardware and applications in real-time. mplab icd 2 also serves as a development programmer for selected picmicro devices. 17.12 pro mate ii universal device programmer the pro mate ii is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features an lcd display for instructions and error messages and a modular detachable socket assembly to support various package types. in stand-alone mode, the pro mate ii device programmer can read, verify and program picmicro devices without a pc connection. it can also set code protection in this mode. 17.13 mplab pm3 device programmer the mplab pm3 is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modular detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand- alone mode, the mplab pm3 device programmer can read, verify and program picmicro devices without a pc connection. it can also set code protection in this mode. mplab pm3 connects to the host pc via an rs- 232 or usb cable. mplab pm3 has high-speed com- munications and optimized algorithms for quick pro- gramming of large memory devices and incorporates an sd/mmc card for file storage and secure data appli- cations.
PIC16F785 ds41249a-page 136 preliminary ? 2004 microchip technology inc. 17.14 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low-cost, prototype programmer. it con- nects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer supports most picmicro devices up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 17.15 picdem 1 picmicro demonstration board the picdem 1 demonstration board demonstrates the capabilities of the pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the sample microcontrollers provided with the picdem 1 demonstration board can be programmed with a pro mate ii device program- mer or a picstart plus development programmer. the picdem 1 demonstration board can be connected to the mplab ice in-circuit emulator for testing. a prototype area extends the circuitry for additional appli- cation components. features include an rs-232 interface, a potentiometer for simulated analog input, push button switches and eight leds. 17.16 picdem.net internet/ethernet demonstration board the picdem.net demonstration board is an internet/ ethernet demonstration board using the pic18f452 microcontroller and tcp/ip firmware. the board supports any 40-pin dip device that conforms to the standard pinout used by the pic16f877 or pic18c452. this kit features a user friendly tcp/ip stack, web server with html, a 24l256 serial eeprom for xmodem download to web pages into serial eeprom, icsp/mplab icd 2 interface con- nector, an ethernet interface, rs-232 interface and a 16 x 2 lcd display. also included is the book and cd-rom ?tcp/ip lean, web servers for embedded systems,? by jeremy bentham 17.17 picdem 2 plus demonstration board the picdem 2 plus demonstration board supports many 18, 28 and 40-pin microcontrollers, including pic16f87x and pic18fxx2 devices. all the neces- sary hardware and software is included to run the dem- onstration programs. the sample microcontrollers provided with the picdem 2 demonstration board can be programmed with a pro mate ii device program- mer, picstart plus development programmer, or mplab icd 2 with a universal programmer adapter. the mplab icd 2 and mplab ice in-circuit emulators may also be used with the picdem 2 demonstration board to test firmware. a prototype area extends the circuitry for additional application components. some of the features include an rs-232 interface, a 2 x 16 lcd display, a piezo speaker, an on-board temperature sensor, four leds and sample pic18f452 and pic16f877 flash microcontrollers. 17.18 picdem 3 pic16c92x demonstration board the picdem 3 demonstration board supports the pic16c923 and pic16c924 in the plcc package. all the necessary hardware and software is included to run the demonstration programs. 17.19 picdem 4 8/14/18-pin demonstration board the picdem 4 can be used to demonstrate the capa- bilities of the 8, 14 and 18-pin pic16xxxx and pic18xxxx mcus, including the pic16f818/819, pic16f87/88, pic16f62xa and the pic18f1320 family of microcontrollers. picdem 4 is intended to showcase the many features of these low pin count parts, including lin and motor control using eccp. special provisions are made for low-power operation with the supercapacitor circuit and jumpers allow on- board hardware to be disabled to eliminate current draw in this mode. included on the demo board are pro- visions for crystal, rc or canned oscillator modes, a five volt regulator for use with a nine volt wall adapter or battery, db-9 rs-232 interface, icd connector for programming via icsp and development with mplab icd 2, 2 x 16 liquid crystal display, pcb footprints for h- bridge motor driver, lin transceiver and eeprom. also included are: header for expansion, eight leds, four potentiometers, three push buttons and a proto- typing area. included with the kit is a pic16f627a and a pic18f1320. tutorial firmware is included along with the user?s guide.
? 2004 microchip technology inc. preliminary ds41249a-page 137 PIC16F785 17.20 picdem 17 demonstration board the picdem 17 demonstration board is an evaluation board that demonstrates the capabilities of several microchip microcontrollers, including pic17c752, pic17c756a, pic17c762 and pic17c766. a pro- grammed sample is included. the pro mate ii device programmer, or the picstart plus development pro- grammer, can be used to reprogram the device for user tailored application development. the picdem 17 demonstration board supports program download and execution from external on-board flash memory. a generous prototype area is available for user hardware expansion. 17.21 picdem 18r pic18c601/801 demonstration board the picdem 18r demonstration board serves to assist development of the pic18c601/801 family of microchip microcontrollers. it provides hardware implementation of both 8-bit multiplexed/demultiplexed and 16-bit memory modes. the board includes 2 mb external flash memory and 128 kb sram memory, as well as serial eeprom, allowing access to the wide range of memory types supported by the pic18c601/801. 17.22 picdem lin pic16c43x demonstration board the powerful lin hardware and software kit includes a series of boards and three picmicro microcontrollers. the small footprint pic16c432 and pic16c433 are used as slaves in the lin communication and feature on-board lin transceivers. a pic16f874 flash microcontroller serves as the master. all three micro- controllers are programmed with firmware to provide lin bus communication. 17.23 pickit tm 1 flash starter kit a complete ?development system in a box?, the pickit flash starter kit includes a convenient multi-section board for programming, evaluation and development of 8/14-pin flash pic ? microcontrollers. powered via usb, the board operates under a simple windows gui. the pickit 1 starter kit includes the user?s guide (on cd rom), pickit 1 tutorial software and code for various applications. also included are mplab ? ide (integrated development environment) software, software and hardware ?tips 'n tricks for 8-pin flash pic ? microcontrollers? handbook and a usb interface cable. supports all current 8/14-pin flash pic microcontrollers, as well as many future planned devices. 17.24 picdem usb pic16c7x5 demonstration board the picdem usb demonstration board shows off the capabilities of the pic16c745 and pic16c765 usb microcontrollers. this board provides the basis for future usb products. 17.25 evaluation and programming tools in addition to the picdem series of circuits, microchip has a line of evaluation kits and demonstration software for these products. k ee l oq evaluation and programming tools for microchip?s hcs secure data products can developers kit for automotive network applications analog design boards and filter design software powersmart battery charging evaluation/ calibration kits irda ? development kit microid development and rflab tm development software seeval ? designer kit for memory evaluation and endurance calculations picdem msc demo boards for switching mode power supply, high-power ir driver, delta sigma adc and flow rate sensor check the microchip web page and the latest product selector guide for the complete list of demonstration and evaluation kits.
PIC16F785 ds41249a-page 138 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds41249a-page 139 PIC16F785 18.0 electrical specifications absolute maximum ratings (?) ambient temperature under bias................................................................................................. .......... -40 to +125c storage temperature ............................................................................................................ ............ -65c to +150c voltage on v dd with respect to v ss ...................................................................................................... -0.3 to +6.5v voltage on mclr with respect to vss ..................................................................................................-0.3 to +13.5v voltage on all other pins with respect to v ss ........................................................................... -0.3v to (v dd + 0.3v) total power dissipation (1) (pdip and soic)................................................................................................... 800 mw total power dissipation (1) (ssop) .................................................................................................................. 600 mw maximum current out of v ss pin ..................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................ 250 ma input clamp current, i ik (v i < 0 or v i > v dd ) ................................................................................................................ 20 ma output clamp current, i ok (vo < 0 or vo >v dd ) .......................................................................................................... 20 ma maximum output current sunk by any i/o pin..................................................................................... ............... 25 ma maximum output current sourced by any i/o pin .................................................................................. ............ 25 ma maximum current sunk by porta, portb, and portc (combined) ........................................................... 200 ma maximum current sourced porta, portb, and portc (combined)........................................................... 200 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd ? i oh } + {(v dd ? v oh ) x i oh } + (v o l x i ol ). ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. note: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50-100 ? should be used when applying a ?low? level to the mclr pin, rather than pulling this pin directly to v ss .
PIC16F785 ds41249a-page 140 preliminary ? 2004 microchip technology inc. figure 18-1: PIC16F785 with analog disabled voltage-frequency graph, -40c t a +125c 5.5 2.0 3.5 2.5 0 3.0 4.0 4.5 5.0 4 frequency (mhz) v dd (volts) note: the shaded region indicates the permissible combinations of voltage and frequency. 816 12 20 10
? 2004 microchip technology inc. preliminary ds41249a-page 141 PIC16F785 18.1 dc characteristics: PIC16F785 -i (industrial), PIC16F785 -e (extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. sym characteristic min typ? max units conditions d001 d001a d001b d001c d001d v dd supply voltage 2.0 2.2 2.5 3.0 4.5 ? ? ? ? ? 5.5 5.5 5.5 5.5 5.5 v v v v v f osc 4 mhz: PIC16F785 with a/d off PIC16F785 with a/d on, 0c to +125c PIC16F785 with a/d on, -40c to +125c 4 mhz f osc 10 mhz 10 mhz f osc 20 mhz d002 v dr ram data retention voltage (1) 1.5* ? ? v device in sleep mode d003 v por v dd voltage above which the internal por releases ?1.8? vsee section 15.3.1 ?power-on reset? for details. d003a v parm v dd voltage below which the internal por rearms ?1.0? vsee section 15.3.1 ?power-on reset? for details. d004 s vdd v dd rise rate to ensure internal power-on reset signal 0.05* ? ? v/ms see section 15.3.1 ?power-on reset? for details. d005 v bor brown-out reset ?2.1? v * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data.
PIC16F785 ds41249a-page 142 preliminary ? 2004 microchip technology inc. 18.2 dc characteristics: PIC16F785-i (industrial) (1,2) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device characteristics min typ? max units conditions v dd note d010 supply current (i dd ) ?9tbda 2.0f osc = 32 khz lp oscillator mode ?18tbda 3.0 ?35tbda 5.0 d011 ? 110 tbd a 2.0 f osc = 1 mhz xt oscillator mode ? 190 tbd a 3.0 ? 330 tbd a 5.0 d012 ? 220 tbd a 2.0 f osc = 4 mhz xt oscillator mode ? 370 tbd a 3.0 ? 0.6 tbd ma 5.0 d013 ? 70 tbd a 2.0 f osc = 1 mhz ec oscillator mode ? 140 tbd a 3.0 ? 260 tbd a 5.0 d014 ? 180 tbd a 2.0 f osc = 4 mhz ec oscillator mode ? 320 tbd a 3.0 ? 580 tbd a 5.0 d015 ? 9 tbd a 2.0 f osc = 31 khz intrc mode ?18tbda 3.0 ?35tbdma 5.0 d016 ? 340 tbd a 2.0 f osc = 4 mhz intosc mode ? 500 tbd a 3.0 ? 0.8 tbd ma 5.0 d017 ? 180 tbd a 2.0 f osc = 4 mhz extrc mode ? 320 tbd a 3.0 ? 580 tbd a 5.0 d018 ? 2.1 tbd ma 4.5 f osc = 20 mhz hs oscillator mode ? 2.4 tbd ma 5.0 legend: tbd = to be determined. ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. these paramet ers are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. 3: the peripheral current is the sum of the base i dd or i pd and the additional current consumed when this peripheral is enabled. the peripheral ? current can be determined by subtracting the base i dd or i pd current from this limit. max values should be used when calculating total current consumption. 4: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd . when a/d is off, it will not consume any current other than leakage current. the power-down current spec includes any such leakage from the a/d module.
? 2004 microchip technology inc. preliminary ds41249a-page 143 PIC16F785 d020 power-down base current (i pd ) (4) ? 8 tbd na 2.0 wdt, bor, comparators, v ref , t1osc, op amps and vr disabled ? 16 tbd na 3.0 ? 33 tbd na 5.0 d021 ? 0.3 tbd a 2.0 wdt current (3) ? 1.8 tbd a 3.0 ? 8.4 tbd a 5.0 d022 ? 58 tbd a 3.0 bor current (3) ? 109 tbd a 5.0 d023 ? 3.3 tbd a 2.0 comparator current (3) cxsp = 1 ? 6.1 tbd a 3.0 ? 200 tbd a 5.0 d023a ? 3.3 tbd a 2.0 comparator current (3) cxsp = 0 ? 6.1 tbd a 3.0 ?35tbda 5.0 d024 ? 58 tbd a 2.0 cv ref current (3) low range ?85tbda 3.0 ? 104 tbd a 5.0 d024a ? 58 tbd a 2.0 cv ref current (3) high range ?85tbda 3.0 ?78tbda 5.0 d025 ? 4.0 tbd a 2.0 t1 o sc current (3) ? 4.6 tbd a 3.0 ? 6.0 tbd a 5.0 d026 ? 1.2 tbd na 3.0 a/d current (3) (not converting) ? 2.2 tbd na 5.0 d027 ? 8 tbd a 2.0 vr current (3) ?10tbda 3.0 ?12tbda 5.0 d028 ? 150 tbd a 3.0 op amp current (3) ? 250 tbd a 5.0 18.2 dc characteristics: PIC16F785-i (industrial) (1,2) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device characteristics min typ? max units conditions v dd note legend: tbd = to be determined. ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. these paramet ers are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. 3: the peripheral current is the sum of the base i dd or i pd and the additional current consumed when this peripheral is enabled. the peripheral ? current can be determined by subtracting the base i dd or i pd current from this limit. max values should be used when calculating total current consumption. 4: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd . when a/d is off, it will not consume any current other than leakage current. the power-down current spec includes any such leakage from the a/d module.
PIC16F785 ds41249a-page 144 preliminary ? 2004 microchip technology inc. 18.3 dc characteristics: PIC16F785-e (extended) (1,2) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40 c t a +125 c for extended param no. device characteristics min typ? max units conditions v dd note d010e supply current (i dd ) ?9tbda 2.0f osc = 32 khz lp oscillator mode ?18tbda 3.0 ?35tbda 5.0 d011e ? 110 tbd a 2.0 f osc = 1 mhz xt oscillator mode ? 190 tbd a 3.0 ? 330 tbd a 5.0 d012e ? 220 tbd a 2.0 f osc = 4 mhz xt oscillator mode ? 370 tbd a 3.0 ? 0.6 tbd ma 5.0 d013e ? 70 tbd a 2.0 f osc = 1 mhz ec oscillator mode ? 140 tbd a 3.0 ? 260 tbd a 5.0 d014e ? 180 tbd a 2.0 f osc = 4 mhz ec oscillator mode ? 320 tbd a 3.0 ? 580 tbd a 5.0 d015e ? 9 tbd a 2.0 f osc = 31 khz intrc mode ?18tbda 3.0 ?35tbdma 5.0 d016e ? 340 tbd a 2.0 f osc = 4 mhz intosc mode ? 500 tbd a 3.0 ? 0.8 tbd ma 5.0 d017e ? 180 tbd a 2.0 f osc = 4 mhz extrc mode ? 320 tbd a 3.0 ? 580 tbd a 5.0 d018e ? 2.1 tbd ma 4.5 f osc = 20 mhz hs oscillator mode ? 2.4 tbd ma 5.0 legend: tbd = to be determined ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. these paramet ers are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. 3: the peripheral current is the sum of the base i dd or i pd and the additional current consumed when this peripheral is enabled. the peripheral ? current can be determined by subtracting the base i dd or i pd current from this limit. max values should be used when calculating total current consumption. 4: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd . when a/d is off, it will not consume any current other than leakage current. the power-down current spec includes any such leakage from the a/d module.
? 2004 microchip technology inc. preliminary ds41249a-page 145 PIC16F785 d020e power-down base current (i pd ) (4) ? 8 tbd na 2.0 wdt, bor, comparators, v ref , t1osc, op amps and vr disabled ? 16 tbd na 3.0 ? 33 tbd na 5.0 d021e ? 0.3 tbd a 2.0 wdt current (3) ? 1.8 tbd a 3.0 ? 8.4 tbd a 5.0 d022e ? 58 tbd a 3.0 bor current (3) ? 109 tbd a 5.0 d023e ? 3.3 tbd a 2.0 comparator current (3) cxsp = 1 ? 6.1 tbd a 3.0 ? 200 tbd a 5.0 d023e ? 3.3 tbd a 2.0 comparator current (3) cxsp = 0 ? 6.1 tbd a 3.0 ?35tbda 5.0 d024e ? 58 tbd a 2.0 cv ref current (3) low range ?85tbda 3.0 ? 104 tbd a 5.0 d024e ? 58 tbd a 2.0 cv ref current (3) high range ?85tbda 3.0 ?78tbda 5.0 d025e ? 4.0 tbd a 2.0 t1 o sc current (3) ? 4.6 tbd a 3.0 ? 6.0 tbd a 5.0 d026e ? 1.2 tbd na 3.0 a/d current (3) (not converting) ? 2.2 tbd na 5.0 d027e ? 8 tbd a 3.0 vr current (3) ?1025 a 3.0 ?1225 a 5.0 d028e ? 150 tbd a 3.0 op amp current (3) ? 250 tbd a 5.0 18.3 dc characteristics: PIC16F785-e (extended) (1,2) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40 c t a +125 c for extended param no. device characteristics min typ? max units conditions v dd note legend: tbd = to be determined ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. these paramet ers are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail to rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature also have an impact on the current consumption. 3: the peripheral current is the sum of the base i dd or i pd and the additional current consumed when this peripheral is enabled. the peripheral ? current can be determined by subtracting the base i dd or i pd current from this limit. max values should be used when calculating total current consumption. 4: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd . when a/d is off, it will not consume any current other than leakage current. the power-down current spec includes any such leakage from the a/d module.
PIC16F785 ds41249a-page 146 preliminary ? 2004 microchip technology inc. 18.4 dc characteristics: PIC16F785 -i (industrial), PIC16F785 -e (extended) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. sym characteristic min typ? max units conditions input low voltage v il i/o ports d030 with ttl buffer v ss ?0.8v4.5v v dd 5.5v d030a v ss ? 0.15 v dd v otherwise d031 with schmitt trigger buffer v ss ?0.2 v dd v entire range d032 mclr , osc1 (rc mode) v ss ?0.2 v dd v d033 osc1 (xt and lp modes) (1) v ss ?0.3v d033a osc1 (hs mode) (1) v ss ?0.3 v dd v input high voltage v ih i/o ports ? d040 d040a with ttl buffer 2.0 (0.25 v dd + 0.8) ? ? v dd v dd v v 4.5v v dd 5.5v otherwise d041 with schmitt trigger buffer 0.8 v dd ?v dd v entire range d042 mclr 0.8 v dd ?v dd v d043 osc1 (xt and lp modes) 1.6 ? v dd v (note 1) d043a osc1 (hs mode) 0.7 v dd ?v dd v (note 1) d043b osc1 (rc mode) 0.9 v dd ?v dd v d070 i pur porta weak pull-up current 50* 250 400* a v dd = 5.0v, v pin = v ss input leakage current (2) d060 i il i/o ports ? 0 . 1 1 av ss v pin v dd , pin at high-impedance d060a analog inputs ? 0 . 1 1av ss v pin v dd d060b v ref ? 0 . 1 1av ss v pin v dd d061 mclr (3) ? 0 . 1 5av ss v pin v dd d063 osc1 ? 0 . 1 5av ss v pin v dd , xt, hs and lp osc configuration output low voltage d080 v ol i/o ports ? ? 0.6 v i ol = 8.5 ma, v dd = 4.5v d083 osc2/clkout (rc mode) ? ? 0.6 v i ol = 1.6 ma, v dd = 4.5v (ind.) i ol = 1.2 ma, v dd = 4.5v (ext.) output high voltage d090 v oh i/o ports v dd ? 0.7 ? ? v i oh = -3.0 ma, v dd = 4.5v d092 osc2/clkout (rc mode) v dd ? 0.7 ? ? v i oh = -1.3 ma, v dd = 4.5v (ind.) i oh = -1.0 ma, v dd = 4.5v (ext.) * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended to use an external clock in rc mode. 2: negative current is defined as current sourced by the pin. 3: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages.
? 2004 microchip technology inc. preliminary ds41249a-page 147 PIC16F785 capacitive loading specs on output pins d100 cosc 2 osc2 pin ? ? 15* pf in xt, hs and lp modes when external clock is used to drive osc1 d101 c io all i/o pins ? ? 50* pf data eeprom memory d120 e d byte endurance 100k 1m ? e/w -40 c t a +85c d120a e d byte endurance 10k 100k ? e/w +85c t a +125c d121 v drw v dd for read/write v min ? 5.5 v using eecon1 to read/write v min = minimum operating voltage d122 t dew erase/write cycle time ? 5 6 ms d123 t retd characteristic retention 40 ? ? year provided no other specifications are violated d124 t ref number of total erase/ write cycles before refresh (1) 1m 10m ? e/w -40 c t a +85c program flash memory d130 e p cell endurance 10k 100k ? e/w -40 c t a +85c d130a e p cell endurance 1k 10k ? e/w +85c t a +125c d131 v pr v dd for read v min ?5.5vv min = minimum operating voltage d132 v pew v dd for erase/write 4.5 ? 5.5 v d133 t pew erase/write cycle time ? 2 2.5 ms d134 t retd characteristic retention 40 ? ? year provided no other specifications are violated 18.4 dc characteristics: PIC16F785 -i (industrial), PIC16F785 -e (extended) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial -40c t a +125c for extended param no. sym characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended to use an external clock in rc mode. 2: negative current is defined as current sourced by the pin. 3: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages.
PIC16F785 ds41249a-page 148 preliminary ? 2004 microchip technology inc. 18.5 timing parameter symbology the timing parameter symbols have been created with one of the following formats: figure 18-2: load conditions figure 18-3: external clock timing 1. tpps2pps 2. tpps t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (high-impedance) v valid l low z high-impedance v dd /2 c l r l pin pin v ss v ss c l r l =464 ? c l = 50 pf for all pins 15 pf for osc2 output load condition 1 load condition 2 osc1 clkout q4 q1 q2 q3 q4 q1 1 2 3 3 4 4
? 2004 microchip technology inc. preliminary ds41249a-page 149 PIC16F785 table 18-1: external clock timing requirements param no. sym characteristic min typ? max units conditions f osc external clkin frequency (1) ? 32.768 ? khz lp mode (complementary input only) dc ? 4 mhz xt mode dc ? 20 mhz hs mode dc ? 20 mhz ec mode oscillator frequency (1) ? 32.768 ? khz lp osc mode ?4 ?mhzintosc mode dc ? 4 mhz rc osc mode 0.1 ? 4 mhz xt osc mode 1? 20mhzhs osc mode 1 t osc external clkin period (1) ? 0.3052 ? s lp mode (complementary input only) 50 ? ns hs osc mode 50 ? ns ec osc mode 250 ? ns xt osc mode oscillator period (1) ? 0.3052 ? s lp osc mode ?250 ? nsintosc mode 250 ? ? ns rc osc mode 250 ? 10,000 ns xt osc mode 50 ? 1,000 ns hs osc mode 2t cy instruction cycle time (1) 200 t cy dc ns t cy = 4/f osc 3 tosl, to sh external clkin (osc1) high external clkin low 2* ? ? s lp oscillator, t osc l/h duty cycle 20* ? ? ns hs oscillator, t osc l/h duty cycle 100 * ? ? ns xt oscillator, t osc l/h duty cycle 4tosr, to sf external clkin rise external clkin fall ? ? 50* ns lp oscillator ? ? 25* ns xt oscillator ? ? 15* ns hs oscillator * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min? values with an external clock applied to osc1 pin. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices.
PIC16F785 ds41249a-page 150 preliminary ? 2004 microchip technology inc. table 18-2: precision internal oscillator parameters figure 18-4: clkout and i/o timing param no. sym characteristic freq tolerance min typ? max units conditions f10 f osc internal calibrated intosc frequency (1) 1% 7.92 8.00 8.08 mhz v dd = 3.5v, 25 c 2% 7.84 8.00 8.16 mhz 2.5v v dd 5.5v 0 c t a +85 c 5% 7.60 8.00 8.40 mhz 2.0v v dd 5.5v -40 c t a +85 c (ind.) -40 c t a +125 c (ext.) f14 t iosc st oscillator wake-up from sleep start-up time* ??tbdtbdsv dd = 2.0v, -40 c to +85 c ??tbdtbdsv dd = 3.0v, -40 c to +85 c ??tbdtbdsv dd = 5.0v, -40 c to +85 c * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: to ensure these oscillator frequency tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1uf and 0.01uf values in parallel are recommended. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 22 23 19 18 15 11 12 16 old value new value table 18-3: clkout and i/o timing requirements param no. sym characteristic min typ? max units conditions 10 tosh2ckl osc1 to clout ? 75 200 ns (note 1) 11 tosh2ckh osc1 to clout ? 75 200 ns (note 1) 12 tckr clkout rise time ? 35 100 ns (note 1) 13 tckf clkout fall time ? 35 100 ns (note 1) 14 tckl2iov clkout to port out valid ? ? 20 ns (note 1) 15 tiov2ckh port in valid before clkout t osc + 200 ns ? ? ns (note 1) 16 tckh2ioi port in hold after clkout 0 ? ? ns (note 1) * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. note 1: measurements are taken in rc mode where clkout output is 4 x t osc .
? 2004 microchip technology inc. preliminary ds41249a-page 151 PIC16F785 figure 18-5: reset, watchdog timer, oscillator start-up timer and power-up timer timing 17 tosh2iov osc1 (q1 cycle) to port out valid ? 50 150 * ns ? ? 300 ns 18 tosh2ioi osc1 (q2 cycle) to port input invalid (i/o in hold time) 100 ? ? ns 19 tiov2osh port input valid to osc1 (i/o in setup time) 0??ns 20 tior port output rise time ? 10 40 ns 21 tiof port output fall time ? 10 40 ns 22 tinp int pin high or low time 25 ? ? ns 23 trbp porta change int high or low time t cy ??ns table 18-3: clkout and i/o timing requirements (continued) param no. sym characteristic min typ? max units conditions * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34
PIC16F785 ds41249a-page 152 preliminary ? 2004 microchip technology inc. figure 18-6: brown-out rese t timing and characteristics table 18-4: reset, watchdog timer, oscillator start-up timer, power-up timer, and brown-out reset requirements param no. sym characteristic min typ? max units conditions 30 t mc lmclr pulse width (low) 2 11 ? 18 ? 24 s ms v dd = 5v, -40c to +85c extended temperature 31 t wdt watchdog timer time-out period (no prescaler) 10 10 17 17 25 30 ms ms v dd = 5v, -40c to +85c extended temperature 32 t ost oscillation start-up timer period ? 1024 t osc ??t osc = osc1 period 33* t pwrt power-up timer period 28* tbd 64 tbd 132* tbd ms ms v dd = 5v, -40c to +85c extended temperature 34 t ioz i/o high-impedance from mclr low or watchdog timer reset ??2.0s 35 v bor brown-out reset voltage 2.025 ? 2.175 v 36 t bor brown-out reset pulse width 100* ? ? s v dd v bor (d005) legend: tbd = to be determined. * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. v bor reset (due to bor) v dd (device in brown-out reset) (device not in brown-out reset) 64 ms time-out (1) 36 note 1: 64 ms delay only if pwrte bit in configuration word is programmed to ? 0 ?.
? 2004 microchip technology inc. preliminary ds41249a-page 153 PIC16F785 figure 18-7: timer0 and timer1 external clock timings table 18-5: timer0 and timer1 external clock requirements param no. sym characteristic min typ? max units conditions 40* tt0h t0cki high pulse width no prescaler 0.5 t cy + 20 ? ? ns with prescaler 10 ? ? ns 41* tt0l t0cki low pulse width no prescaler 0.5 t cy + 20 ? ? ns with prescaler 10 ? ? ns 42* tt0p t0cki period greater of: 20 or t cy + 40 n ? ? ns n = prescale value (2, 4, ..., 256) 45* tt1h t1cki high time synchronous, no prescaler 0.5 t cy + 20 ? ? ns synchronous, with prescaler 15 ? ? ns asynchronous 30 ? ? ns 46* tt1l t1cki low time synchronous, no prescaler 0.5 t cy + 20 ? ? ns synchronous, with prescaler 15 ? ? ns asynchronous 30 ? ? ns 47* tt1p t1cki input period synchronous greater of: 30 or t cy + 40 n ? ? ns n = prescale value (1, 2, 4, 8) asynchronous 60 ? ? ns 48 ft1 timer1 oscillator input frequency range (oscillator enabled by setting bit t1oscen) dc ? 200* khz 49 tckeztmr1 delay from external clock edge to timer increment 2 t osc *?7 t osc * ? * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. t0cki t1cki 40 41 42 45 46 47 49 tmr0 or tmr1
PIC16F785 ds41249a-page 154 preliminary ? 2004 microchip technology inc. figure 18-8: capture/compare/pwm timings (ccp) table 18-6: capture/compare/pwm requirements (ccp) param no. symbol characteristic min typ? max units conditions 50* tccl ccp1 input low time no prescaler 0.5t cy + 20 ?? ns with prescaler 20 ? ? ns 51* tcch ccp1 input high time no prescaler 0.5t cy + 20 ?? ns with prescaler 20 ? ? ns 52* tccp ccp1 input period 3t cy + 40 n ? ? ns n = prescale value (1,4 or 16) 53* tccr ccp1 output rise time ? 25 50 ns 54* tccf ccp1 output fall time ? 25 45 ns * these parameters are characterized but not tested. ? data in ?typ? column is at 5v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note: refer to figure 18-2 for load conditions. (capture mode) 50 51 52 53 54 ccp1 (compare or pwm mode) ccp1
? 2004 microchip technology inc. preliminary ds41249a-page 155 PIC16F785 table 18-7: comparator specifications table 18-8: comparator voltage reference (v ref ) specifications table 18-9: voltage (vr) reference specifications comparator specifications standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c param no. symbol characteristics min typ max units comments c01 v os input offset voltage ? 2 5mv c02 v cm input common mode voltage 0 ? v dd ? 1.5 v c03 i lc input leakage current ? ? 200* na c04 c mrr common mode rejection ratio +70* ? ? db c05 t rt response time (1) ? ? ? ? 20* 40* ns ns internal output to pin * these parameters are characterized but not tested. note 1: response time measured with one comparator input at (v dd ? 1.5)/2, while the other input transitions from v ss to v dd ? 1.5v. comparator voltage reference specifications standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c param no. symbol characteristics min typ max units comments cv01 cv res resolution ? ? v dd /24* v dd /32 ? ? lsb lsb low range (vrr = 1 ) high range (vrr = 0 ) cv02 absolute accuracy ? ? ? ? 1/4* 1/2* lsb lsb low range (vrr = 1 ) high range (vrr = 0 ) cv03 unit resistor value (r) ? 2k* ? ? cv04 settling time (1) ?? 10*s * these parameters are characterized but not tested. note 1: settling time measured while vrr = 1 and vr<3:0> transitions from 0000 to 1111 . vr voltage reference specifications standard operating conditions (unless otherwise stated) operating temperature -40c t a +125c param no. symbol characteristics min typ max units comments vr01 v rout vr voltage output tbd 1.200 tbd v vr02 tcv out voltage drift temperature coefficient ? 150 tbd ppm/ c vr03 ? v rout / ? v dd voltage drift with respect to v dd regulation ?200? v/v vr04 t stable settling time ? 10 100* s legend: tbd = to be determined * these parameters are characterized but not tested.
PIC16F785 ds41249a-page 156 preliminary ? 2004 microchip technology inc. table 18-10: operational ampl ifier (opa) dc specifications table 18-11: operational amplifier (opa) ac specifications opa dc characteristics standard operating conditions (unless otherwise stated) v cm = 0v, vout = v dd /2, v dd = 5v, v ss = 0v, c l = 50pf, r l = 100k operating temperature -40c t a +125c param no. symbol characteristics min typ max units comments opa01* v os input offset voltage ? 5?mv opa02* opa03* i b i os input current and impedance input bias current input offset bias current ? ? 2* 1* ? ? na pa opa04* opa05* v cm cmr common mode common mode input range common mode rejection v ss tbd ? 70 v dd ? 1.4 ? v db v dd = 5v v cm = v dd /2, freq = dc opa06a* opa06b* a ol a ol open loop gain dc open loop gain dc open loop gain ? ? 90 60 ? ? db db no load standard load opa07* opa08* vout isc output output voltage swing output short circuit current v ss + 50 ? ? 25 v dd ? 50 tbd mv ma to v dd /2 (20 k ? connected to v dd , 20 k ? + 20 pf to vss) opa10 psr power supply power supply rejection 80 ? ? db legend: tbd = to be determined * these parameters are characterized but not tested. opa ac characteristics standard operating conditions (unless otherwise stated) v cm = 0v, vout = v dd /2, v dd = 5v, v ss = 0v, c l = 50pf, r l = 100k operating temperature -40c t a +125c param no. symbol characteristics min typ max units comments opa11* gbwp gain bandwidth product ? 3 ? mhz opa12* t on turn on time ? 10 tbd s opa13* m phase margin ? 60 ? deg opa14* sr slew rate 2 ? ? v/ s legend: tbd = to be determined * these parameters are characterized but not tested.
? 2004 microchip technology inc. preliminary ds41249a-page 157 PIC16F785 table 18-12: PIC16F785 a/d converter characteristics : param no. sym characteristic min typ? max units conditions a01 n r resolution ? ? 10 bits bit a02 e abs total absolute error* (1) ?? 1lsbv ref = 5.0v a03 e il integral error ? ? 1lsbv ref = 5.0v a04 e dl differential error ? ? 1 lsb no missing codes to 10 bits v ref = 5.0v a05 e fs full scale range 2.2* ? 5.5* v a06 e off offset error ? ? 1lsbv ref = 5.0v a07 e gn gain error ? ? 1lsbv ref = 5.0v a10 ? monotonicity ? guaranteed (2) ??v ss v ain v ref a20 a20a v ref reference voltage 2.2 (4) 2.5 ?? v dd + 0.3 v absolute minimum to ensure 10-bit accuracy a25 v ain analog input voltage v ss ?v ref (5) v a30 z ain recommended impedance of analog voltage source ?? 10k ? a50 i ref v ref input current* (3) 10 ? ? ? 1000 10 a a during v ain acquisition. based on differential of v hold to v ain . during a/d conversion cycle. * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: total absolute error includes integral, differential, offset and gain errors. 2: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes. 3: v ref current is from external v ref or v dd pin, whichever is selected as reference input. 4: only limited when v dd is at or below 2.5v. if v dd is above 2.5v, v ref is allowed to go as low as 1.0v. 5: analog input voltages are allowed up to v dd , however the conversion accuracy is limited to v ss to v ref .
PIC16F785 ds41249a-page 158 preliminary ? 2004 microchip technology inc. figure 18-9: PIC16F785 a/d conversion timing (normal mode) table 18-13: PIC16F785 a/d conversion requirements param no. sym characteristic min typ? max units conditions 130 t ad a/d clock period 1.6 ? ? s t osc -based, v ref 3.0v 3.0* ? ? s t osc -based, v ref full range 130 t ad a/d internal rc oscillator period 3.0* 6.0 9.0* s adcs<1:0> = 11 (rc mode) at v dd = 2.5v 2.0* 4.0 6.0* s at v dd = 5.0v 131 t cnv conversion time (not including acquisition time) (1) ?11?t ad set go bit to new data in a/d result register 132 t acq acquisition time (note 2) 5* 11.5 ? ? ? s s the minimum time is the amplifier settling time. this may be used if the ?new? input voltage has not changed by more than 1 lsb (i.e., 4.1 mv @ 4.096v) from the last sampled voltage (as stored on c hold ). 134 t go q4 to a/d clock start ?t osc /2 ? ? if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adresh and adresl registers may be read on the following t cy cycle. 2: see table 12-1 for minimum conditions. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data 987 3210 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 t cy 6 134 (t osc /2) (1) 1 t cy
? 2004 microchip technology inc. preliminary ds41249a-page 159 PIC16F785 figure 18-10: PIC16F785 a/d conversion timing (sleep mode) table 18-14: PIC16F785 a/d conversion requirements (sleep mode) param no. sym characteristic min typ? max units conditions 130 t ad a/d internal rc oscillator period 3.0* 6.0 9.0* s adcs<1:0> = 11 (rc mode) at v dd = 2.5v 2.0* 4.0 6.0* s at v dd = 5.0v 131 t cnv conversion time (not including acquisition time) (1) ?11?t ad 132 t acq acquisition time (note 2) 5* 11.5 ? ? ? s s the minimum time is the amplifier settling time. this may be used if the ?new? input voltage has not changed by more than 1 lsb (i.e., 4.1 mv @ 4.096v) from the last sampled voltage (as stored on c hold ). 134 t go q4 to a/d clock start ?t osc /2 + t cy ? ? if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25 c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adres register may be read on the following t cy cycle. 2: see table 12-1 for minimum conditions. 131 130 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data 9 7 3210 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 134 6 8 132 1 t cy (t osc /2 + t cy ) (1) 1 t cy
PIC16F785 ds41249a-page 160 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds41249a-page 161 PIC16F785 19.0 packaging information 19.1 package marking information xxxxxxxxxxxxxx 20-lead pdip (dip) example xxxxxxxxxxxxxx yywwnnn PIC16F785 0415017 xxxxxxxxxxx 20-lead soic xxxxxxxxxxx yywwnnn example PIC16F785 0415017 20-lead ssop xxxxxxxxxxx yywwnnn example legend: xx...x customer specific information* y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * standard picmicro device marking consists of microchip part number, year code, week code, and traceability code. for picmicro device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. PIC16F785 0415017 xxxxxxxxxxx -i/ss -e/so -i/p
PIC16F785 ds41249a-page 162 preliminary ? 2004 microchip technology inc. 19.2 package details the following sections give the technical details of the packages. 20-lead plastic dual in-line (p) ? 300 mil body (pdip ) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 10.92 9.40 7.87 .430 .370 .310 eb overall row spacing 0.56 0.46 0.36 .022 .018 .014 b lower lead width 1.65 1.52 1.40 .065 .060 .055 b1 upper lead width 0.38 0.29 0.20 .015 .012 .008 c lead thickness 3.56 3.30 3.05 .140 .130 .120 l tip to seating plane 26.42 26.24 26.04 1.040 1.033 1.025 d overall length 6.60 6.35 6.10 .260 .250 .240 e1 molded package width 8.26 7.87 7.49 .325 .310 .295 e shoulder to shoulder width 0.38 .015 a1 base to seating plane 3.68 3.30 2.92 .145 .130 .115 a2 molded package thickness 4.32 3.94 3.56 .170 .155 .140 a top to seating plane 2.54 .100 p pitch 20 20 n number of pins max nom min max nom min dimension limits millimeters inches* units 1 2 d n e1 c eb e p a2 l b1 b a a1 * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-001 drawing no. c04-019 significant characteristic
? 2004 microchip technology inc. preliminary ds41249a-page 163 PIC16F785 20-lead plastic small outline (so) ? wide, 300 mil body (soic ) * controlling parameter notes: dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010? (0.254mm) per side. jedec equivalent: ms-013 drawing no. c04-094 foot angle 048048 15 12 0 15 12 0 mold draft angle bottom 15 12 0 15 12 0 mold draft angle top 0.51 0.42 0.36 .020 .017 .014 b lead width 0.33 0.28 0.23 .013 .011 .009 c lead thickness 1.27 0.84 0.41 .050 .033 .016 l foot length 0.74 0.50 0.25 .029 .020 .010 h chamfer distance 13.00 12.80 12.60 .512 .504 .496 d overall length 7.59 7.49 7.39 .299 .295 .291 e1 molded package width 10.67 10.34 10.01 .420 .407 .394 e overall width 0.30 0.20 0.10 .012 .008 .004 a1 standoff 2.39 2.31 2.24 .094 .091 .088 a2 molded package thickness 2.64 2.50 2.36 .104 .099 .093 a overall height 1.27 .050 p pitch 20 20 n number of pins max nom min max nom min dimension limits millimeters inches* units h l c 45 1 2 d p n b e e1 a2 a a1 significant characteristic
PIC16F785 ds41249a-page 164 preliminary ? 2004 microchip technology inc. 20-lead plastic shrink small outline (ss) ? 209 mil body, 5.30 mm (ssop) 0.38 - 0.22 .015 - .009 b lead width 8 4 0 8 4 0 ? foot angle 0.25 - 0.09 .010 - .004 c lead thickness 0.95 0.75 0.55 .037 .030 .022 l foot length 7.50 7.20 6.90 .295 .283 .272 d overall length 5.60 5.30 5.00 .220 .209 .197 e1 molded package width 8.20 7.80 7.40 .323 .307 .291 e overall width - - 0.05 - - .002 a1 standoff 1.85 1.75 1.65 .073 .069 .065 a2 molded package thickness 2.00 - - .079 - - a overall height 0.65 .026 p pitch 20 20 n number of pins max nom min max nom min dimension limits millimeters* inches units 2 1 d p n b e e1 l c ? a2 a a1 shall not exceed .010" (0.254mm) per side. dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions notes: jedec equivalent: mo-150 drawing no. c04-072 *controlling parameter revised 11/03/03
? 2004 microchip technology inc. preliminary ds41249a-page 165 PIC16F785 appendix a: data sheet revision history revision a this is a new data sheet. appendix b: migrating from other picmicro ? devices this discusses some of the issues in migrating from the pic16f684 picmicro device to the PIC16F785. b.1 pic16f684 to PIC16F785 table b-1: feature comparison feature pic16f684 PIC16F785 max operating speed 20 mhz 20 mhz max program memory (words) 2048 2048 sram (bytes) 128 128 a/d resolution 10-bit 10-bit data eeprom (bytes) 256 256 timers (8/16-bit) 2/1 2/1 oscillator modes 8 8 brown-out reset y y internal pull-ups ra0/1/2/4/5 m clr ra0/1/2/3/4/5 m clr interrupt-on-change ra0/1/2/3/4/5 ra0/1/2/3/4/5 comparator 2 ccp eccp y op amps n 2 pwm n 2 phase ultra low-power wake-up yn extended wdt y y software control option of wdt/bor yy intosc frequencies 32 khz - 8mhz 32 khz - 8mhz clock switching y y
PIC16F785 ds41249a-page 166 preliminary ? 2004 microchip technology inc. notes:
? 2004 microchip technology inc. preliminary ds41249a-page 167 PIC16F785 index a a/d ...................................................................................... 77 acquisition requirements ........................................... 83 analog port pins ......................................................... 78 associated registers.................................................... 86 block diagram............................................................. 77 calculating acquisition time....................................... 83 channel selection....................................................... 78 configuration and operation....................................... 78 configuring.................................................................. 82 configuring interrupt ................................................... 82 conversion clock........................................................ 78 effects of a reset........................................................ 86 internal sampling switch (r ss ) impedance................ 83 operation during sleep .............................................. 85 output format............................................................. 79 reference voltage (v ref )........................................... 78 source impedance...................................................... 83 special event trigger.................................................. 86 specifications............................................ 157, 158, 159 starting a conversion ................................................. 79 using the eccp trigger ............................................. 86 absolute maximum ratings .............................................. 139 ac characteristics load conditions ........................................................ 148 adcon0 register............................................................... 81 adcon1 register............................................................... 81 analog-to-digital converter. see a/d ansel register.................................................................. 80 assembler mpasm assembler................................................... 133 b block diagrams (ccp) capture mode operation ................................. 56 a/d .............................................................................. 77 analog input model ..................................................... 84 ccp pwm................................................................... 58 clock source............................................................... 23 comparator 1 .............................................................. 62 comparator 2 .............................................................. 64 compare ..................................................................... 57 cvref........................................................................... 69 fail-safe clock monitor (fscm) ................................. 30 in-circuit serial programming connections.............. 121 interrupt logic ........................................................... 114 mclr circuit............................................................. 106 on-chip reset circuit ............................................... 105 opa module................................................................ 73 pic16f684.................................................................... 5 ra0 pin....................................................................... 36 ra1 pin....................................................................... 36 ra2 pin....................................................................... 37 ra3 pin....................................................................... 37 ra4 pin....................................................................... 38 ra5 pin....................................................................... 38 rb4 and rb5 pins. ..................................................... 41 rb6 pin....................................................................... 41 rb7 pin....................................................................... 41 rc0 and rc1 pins...................................................... 41 rc0, rc6 and rc7 pins ............................................ 44 rc1 pin....................................................................... 44 rc2 and rc3 pins...................................................... 45 rc4 pin....................................................................... 45 rc5 pin ...................................................................... 46 resonator operation .................................................. 25 timer1 ........................................................................ 49 timer2 ........................................................................ 54 tmr0/wdt prescaler ................................................ 47 two phase pwm complementary output mode ............................ 96 simplified diagram ............................................. 88 single phase example ....................................... 94 vr reference ............................................................. 72 watchdog timer (wdt)............................................ 117 brown-out reset (bor).................................................... 107 associated registers ................................................. 108 calibration ................................................................ 107 specifications ........................................................... 152 timing and characteristics ....................................... 152 c c compilers mplab c17.............................................................. 134 mplab c18.............................................................. 134 mplab c30.............................................................. 134 calibration bits.................................................................. 103 capture module. see capture/compare/pwm (ccp) capture/compare/pwm (ccp) .......................................... 55 associated registers ................................................... 60 associated registers w/ capture/compare/timer1..... 57 capture mode............................................................. 56 ccp1 pin configuration ............................................. 56 compare mode........................................................... 57 ccp1 pin configuration ..................................... 57 software interrupt mode ..................................... 57 special event trigger and a/d conversions ...... 57 special trigger output........................................ 57 timer1 mode selection....................................... 57 prescaler .................................................................... 56 pwm mode................................................................. 58 duty cycle .......................................................... 58 effects of reset .................................................. 59 example pwm frequencies and resolutions .... 59 operation in power managed modes ................. 59 operation with fail-safe clock monitor .............. 59 setup for operation ............................................ 59 setup for pwm operation .................................. 59 specifications ........................................................... 154 timer resources ........................................................ 55 ccp. see capture/compare/pwm (ccp) ccp1con register............................................................ 55 ccpr1h register............................................................... 55 ccpr1l register ............................................................... 55 clock sources..................................................................... 23 cm1con0 .......................................................................... 63 cm2con1 .......................................................................... 66 code examples assigning prescaler to timer0.................................... 48 assigning prescaler to wdt....................................... 48 changing between capture prescalers ..................... 56 data eeprom read................................................ 101 data eeprom write ................................................ 101 eeprom write verify .............................................. 101 indirect addressing..................................................... 22 initializing a/d............................................................. 82 initializing porta ...................................................... 33 initializing portb ...................................................... 40
PIC16F785 ds41249a-page 168 preliminary ? 2004 microchip technology inc. initializing portc....................................................... 43 interrupt context saving ........................................... 116 code protection ................................................................ 121 comparator module ............................................................ 61 associated registers.................................................... 72 c1 output state versus input conditions ................... 61 c2 output state versus input conditions ................... 64 comparator interrupts ................................................. 67 effects of a reset ..................................................... 67 comparator voltage reference (cv ref ) specifications............................................................ 155 comparators c2out as t1 gate ..................................................... 50 specifications............................................................ 155 compare module. see capture/compare/pwm (ccp) config register.............................................................. 104 configuration bits.............................................................. 103 cpu features ................................................................... 103 d data eeprom memory associated registers.................................................. 102 code protection .................................................. 99, 102 data memory......................................................................... 9 dc characteristics extended and industrial ............................................ 146 industrial and extended ............................................ 141 demonstration boards picdem 1 ................................................................. 136 picdem 17 ............................................................... 137 picdem 18r ............................................................ 137 picdem 2 plus ......................................................... 136 picdem 3 ................................................................. 136 picdem 4 ................................................................. 136 picdem lin ............................................................. 137 picdem usb............................................................ 137 picdem.net internet/ethernet .................................. 136 development support ....................................................... 133 device overview ................................................................... 5 e eeadr register ................................................................. 99 eecon1 register ............................................................. 100 eecon2 register ............................................................. 100 eedat register.................................................................. 99 eeprom data memory avoiding spurious write............................................ 101 reading..................................................................... 101 write verify ............................................................... 101 writing ....................................................................... 101 electrical specifications .................................................... 139 errata .................................................................................... 3 evaluation and programming tools .................................. 137 f fail-safe clock monitor....................................................... 30 fail-safe condition clearing ....................................... 31 reset and wake-up from sleep .................................. 31 firmware instructions........................................................ 123 fuses. see configuration bits g general purpose register file.............................................. 9 i id locations...................................................................... 121 in-circuit debugger........................................................... 122 in-circuit serial programming (icsp)............................... 121 indirect addressing, indf and fsr registers..................... 22 instruction format............................................................. 123 instruction set................................................................... 123 addlw..................................................................... 125 addwf..................................................................... 125 andlw..................................................................... 125 andwf..................................................................... 125 bcf .......................................................................... 125 bsf........................................................................... 125 btfsc ...................................................................... 125 btfss ...................................................................... 125 call......................................................................... 126 clrf ........................................................................ 126 clrw ....................................................................... 126 clrwdt .................................................................. 126 comf ....................................................................... 126 decf ........................................................................ 126 decfsz ................................................................... 126 goto ....................................................................... 127 incf ......................................................................... 127 incfsz..................................................................... 127 iorlw ...................................................................... 127 iorwf...................................................................... 127 movf ....................................................................... 127 movlw .................................................................... 128 movwf .................................................................... 128 nop .......................................................................... 128 retfie ..................................................................... 128 retlw ..................................................................... 129 return................................................................... 129 rlf ........................................................................... 129 rrf .......................................................................... 130 sleep ...................................................................... 130 sublw ..................................................................... 130 subwf..................................................................... 131 swapf ..................................................................... 131 tris ......................................................................... 131 xorlw .................................................................... 132 xorwf .................................................................... 132 summary table ........................................................ 124 intcon register................................................................ 17 internal oscillator block intosc specifications ................................................... 150 internal sampling switch (r ss ) impedance........................ 83 interrupts........................................................................... 113 (ccp) compare .......................................................... 57 a/d.............................................................................. 82 associated registers ................................................. 115 comparator................................................................. 67 context saving ......................................................... 116 data eeprom memory write .................................. 100 interrupt-on-change .................................................... 35 oscillator fail (osf) ................................................... 30 porta interrupt-on-change..................................... 114 ra2/int .................................................................... 114 tmr0 ........................................................................ 114 tmr1 .......................................................................... 50 tmr2 to pr2 match ............................................. 53, 54 intosc specifications ..................................................... 150 ioca (interrupt-on-change) ................................................ 35 ioca register..................................................................... 35
? 2004 microchip technology inc. preliminary ds41249a-page 169 PIC16F785 l load conditions ................................................................ 148 m mclr ................................................................................ 106 internal ...................................................................... 106 memory organization............................................................ 9 data .............................................................................. 9 data eeprom memory.............................................. 99 program ........................................................................ 9 migrating from other picmicro devices ............................ 165 mplab asm30 assembler, linker, librarian ................... 134 mplab icd 2 in-circuit debugger ................................... 135 mplab ice 2000 high-performance universal in-circuit em- ulator ......................................................................... 135 mplab ice 4000 high-performance universal in-circuit em- ulator ......................................................................... 135 mplab integrated development environment software .. 133 mplab pm3 device programmer .................................... 135 mplink object linker/mplib object librarian ................ 134 o opa module associated registers .................................................. 75 opa1con .......................................................................... 74 opa2con .......................................................................... 74 opcode field descriptions ............................................. 123 operational amplifier (opa) module................................... 73 operational amplifier (opa) module ................................... 73 option_reg register ...................................................... 16 osccon register.............................................................. 32 oscillator associated registers.................................................... 32 oscillator specifications.................................................... 149 oscillator start-up timer (ost) specifications............................................................ 152 oscillator switching fail-safe clock monitor............................................... 30 two-speed clock start-up.......................................... 29 p packaging ......................................................................... 161 marking ..................................................................... 161 packaging details ..................................................... 162 pcl and pclath ............................................................... 21 stack ........................................................................... 21 pcon register ................................................................. 108 pickit 1 flash starter kit................................................... 137 picstart plus development programmer ..................... 136 pie1 register...................................................................... 18 pin diagram .......................................................................... 2 pinout descriptions pic16f684.................................................................... 6 pir1 register...................................................................... 19 porc rc2............................................................................. 45 porta................................................................................ 33 additional pin functions ............................................. 34 interrupt-on-change ............................................ 35 weak pull-up ...................................................... 34 associated registers.................................................... 39 pin descriptions and diagrams................................... 36 ra0 ............................................................................. 36 ra1 ............................................................................. 36 ra2 ............................................................................. 37 ra3 ............................................................................. 37 ra4............................................................................. 38 ra5............................................................................. 38 specifications ........................................................... 150 portb ............................................................................... 40 associated registers ................................................... 42 pin descriptions and diagrams .................................. 41 rb4............................................................................. 41 rb5............................................................................. 41 rb6............................................................................. 41 rb7............................................................................. 41 portc ............................................................................... 43 associated registers ............................................. 32, 46 pin descriptions and diagrams .................................. 44 rc0 ............................................................................ 44 rc1 ............................................................................ 44 rc3 ............................................................................ 45 rc4 ............................................................................ 45 rc5 ............................................................................ 46 rc6 ............................................................................ 44 rc7 ............................................................................ 44 specifications ........................................................... 150 power-down mode (sleep)............................................... 119 power-up timer (pwrt) .................................................. 106 specifications ........................................................... 152 power-up timing delays................................................... 108 precision internal oscillator parameters .......................... 150 prescaler shared wdt/timer0................................................... 48 switching prescaler assignment ................................ 48 pro mate ii universal device programmer ................... 135 product identification ........................................................ 176 program memory .................................................................. 9 map and stack.............................................................. 9 programming, device instructions.................................... 123 pwm. see two phase pwm pwmclk register.............................................................. 90 pwmcon0 register........................................................... 89 pwmcon1 register........................................................... 95 pwmph1 register.............................................................. 91 pwmph2 register.............................................................. 92 r read-modify-write operations ......................................... 123 refcon (vr control) ........................................................ 71 register ioca (interrupt-on-change) ........................................ 35 wpua (weak pullup).................................................. 34 registers adcon0 (a/d control 0)............................................ 81 adcon1 (a/d control 1)............................................ 81 ansel (analog select) .............................................. 80 ccp1con (ccp operation) ...................................... 55 ccpr1h..................................................................... 55 ccpr1l ..................................................................... 55 cm1con0 (c1 control) ............................................. 63 cm1con0 (c2 control) cm2con0 .......................................................... 65 cm2con1 (c2 control) .............................................. 66 config (configuration word) ................................. 104 data memory map ...................................................... 10 eeadr (eeprom address) ...................................... 99 eecon1 (eeprom control 1) ................................ 100 eecon2 (eeprom control 2) ................................ 100 eedat (eeprom data) ............................................ 99 intcon (interrupt control) ........................................ 17 ioca (interrupt-on-change porta) .......................... 35
PIC16F785 ds41249a-page 170 preliminary ? 2004 microchip technology inc. opamp control register (opacon) ......................... 74 option_reg (option) .............................................. 16 osccon (oscillator control) ..................................... 32 pcon (power control) ............................................. 108 pie1 (peripheral interrupt enable 1) ........................... 18 pir1 (peripheral interrupt register 1) ........................ 19 porta........................................................................ 33 portb........................................................................ 40 portc ....................................................................... 43 pwmclk (pwm clock control) ................................... 90 pwmcon0 (pwm control 0) ...................................... 89 pwmcon1 (pwm control 1) ...................................... 95 pwmph1 (pwm phase 1 control) .............................. 91 pwmph2 (pwm phase 2 control) .............................. 92 refcon (vr control)................................................. 71 reset values (special registers) ............................... 112 special function registers............................................. 9 special register summary ....................... 11, 12, 13, 14 status .......................................................................... 15 t1con (timer1 control)............................................. 51 t2con (timer2 control)............................................. 53 trisa (tristate porta)............................................. 34 trisb (tristate portb)............................................. 40 trisc (tristate portc) ............................................ 43 wdtcon (watchdog timer control)........................ 118 wpua (weak pull-up porta) ................................... 34 resets ............................................................................... 105 power-on reset ....................................................... 106 revision history ................................................................ 165 rrf instruction ................................................................. 130 s sleep instruction ............................................................. 130 software simulator (mplab sim)..................................... 134 software simulator (mplab sim30)................................. 134 special event trigger.......................................................... 86 special function registers..................................................... 9 status register.................................................................... 15 sublw instruction............................................................ 130 subwf instruction............................................................ 131 swapf instruction............................................................ 131 t time-out sequence........................................................... 108 timer0 ................................................................................. 47 associated registers.................................................... 48 external clock............................................................. 48 interrupt....................................................................... 47 operation .................................................................... 47 prescaler..................................................................... 48 specifications............................................................ 153 timer1 ................................................................................. 49 associated registers.................................................... 52 asynchronous counter mode ..................................... 52 reading and writing ........................................... 52 interrupt....................................................................... 50 modes of operations................................................... 50 operation during sleep .............................................. 52 oscillator ..................................................................... 52 prescaler..................................................................... 50 specifications............................................................ 153 timer1 gate inverting gate ..................................................... 50 selecting source................................................. 50 tmr1h register ......................................................... 49 tmr1l register.......................................................... 49 timer2................................................................................. 53 associated registers ................................................... 54 operation .................................................................... 53 postscaler................................................................... 53 pr2 register .............................................................. 53 prescaler .................................................................... 53 tmr2 register............................................................ 53 tmr2 to pr2 match interrupt............................... 53, 54 timing diagrams a/d conversion......................................................... 158 a/d conversion (sleep mode) .................................. 159 brown-out reset (bor)............................................ 152 brown-out reset situations ...................................... 107 capture/compare/pwm (ccp) ................................ 154 clkout and i/o ...................................................... 150 external clock........................................................... 148 fail-safe clock monitor (fscm)................................. 31 int pin interrupt ....................................................... 115 reset, wdt, ost and power-up timer ................... 151 time-out sequence case 1 .............................................................. 109 case 2 .............................................................. 109 case 3 .............................................................. 109 timer0 and timer1 external clock ........................... 153 timer1 incrementing edge ......................................... 50 two phase pwm auto-shutdown ................................................... 93 complementary output ...................................... 96 startup ................................................................ 93 system timing.................................................... 92 two speed start-up.................................................... 30 wake-up from interrupt............................................. 120 timing parameter symbology .......................................... 148 tris instruction ................................................................ 131 trisa register................................................................... 34 trisb register................................................................... 40 trisc register................................................................... 43 two phase pwm ................................................................ 87 activating .................................................................... 87 active output level ...................................................... 88 associated registers ................................................... 97 auto shutdown ............................................................ 88 clock control (pwmclk)............................................ 90 control register 0 (pwmcon0)................................. 89 control register 1 (pwmcon1)................................. 95 master/slave operation .............................................. 87 output blanking .......................................................... 87 phase 1 control (pwmph1)........................................ 91 phase 2 control (pwmph1)........................................ 92 pwm duty cycle......................................................... 87 pwm frequency ......................................................... 87 pwm period................................................................ 87 pwm phase................................................................ 87 pwm phase resolution ............................................... 87 shutdown.................................................................... 88 two-speed clock start-up mode........................................ 29 v voltage references ............................................................ 69 associated registers ................................................... 72 configuring cvref ....................................................... 69 cvref (comparator reference)................................... 69 cvref accuracy........................................................... 69 fixed vr reference..................................................... 71 vr stabilization .......................................................... 72 v ref . s ee a/d reference voltage
? 2004 microchip technology inc. preliminary ds41249a-page 171 PIC16F785 w wake-up using interrupts ................................................. 119 watchdog timer (wdt) .................................................... 117 associated registers.................................................. 118 clock source............................................................. 117 modes ....................................................................... 117 period........................................................................ 117 specifications............................................................ 152 wdtcon register ........................................................... 118 wpua (weak pullup) ........................................................... 34 wpua register................................................................... 34 www, on-line support ....................................................... 3 x xorlw instruction ........................................................... 132 xorwf instruction ........................................................... 132
PIC16F785 ds41249a-page 172 preliminary ? 2004 microchip technology inc. notes:
PIC16F785 ds41249a-page 173 preliminary ? 2004 microchip technology inc. on-line support microchip provides on-line support on the microchip world wide web site. the web site is used by microchip as a means to make files and information easily available to customers. to view the site, the user must have access to the internet and a web browser, such as netscape ? or microsoft ? internet explorer. files are also available for ftp download from our ftp site. connecting to the microchip internet web site the microchip web site is available at the following url: www.microchip.com the file transfer site is available by using an ftp service to connect to: ftp://ftp.microchip.com the web site and file transfer site provide a variety of services. users may download files for the latest development tools, data sheets, application notes, user's guides, articles and sample programs. a vari- ety of microchip specific business information is also available, including listings of microchip sales offices, distributors and factory representatives. other data available for consideration is: latest microchip press releases technical support section with frequently asked questions design tips device errata job postings microchip consultant program member listing links to other useful web sites related to microchip products conferences for products, development systems, technical information and more listing of seminars and events systems information and upgrade hot line the systems information and upgrade line provides system users a listing of the latest versions of all of microchip's development systems software products. plus, this line provides information on how customers can receive the most current upgrade kits. the hot line numbers are: 1-800-755-2345 for u.s. and most of canada, and 1-480-792-7302 for the rest of the world. 042003
? 2004 microchip technology inc. preliminary ds41249a-page 174 PIC16F785 reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds41249a PIC16F785 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2004 microchip technology inc. preliminary ds41249a-page 175 PIC16F785 product identification system to order or obtain information, e.g. , on pricing or delivery, refer to the factory or the listed sales office. sales and support part no. x /xx xxx pattern package temperature range device device 16f: standard v dd range 16ft: (tape and reel) temperature range i = -40 c to +85 c e= -40 c to +125 c package p = pdip so = soic (gull wing, 300 mil body) ss = ssop(5.3 mm) pattern 3-digit pattern code for qtp (blank otherwise) examples: a) PIC16F785 ? e/p 301 = extended temp., pdip package, 20 mhz, qtp pattern #301 b) PIC16F785 ? i/so = industrial temp., soic package, 20 mhz data sheets products supported by a preliminary data sheet may have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: 1. your local microchip sales office 2. the microchip corporate literature center u.s. fax: (480) 792-7277 3. the microchip worldwide site (www.microchip.com) please specify which device, revision of silicon and data sheet (include literature #) you are using. new customer notification system register on our web site (www.microchip.com/cn) to receive the most current information on our products.
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